SFR 0xfeb0: Undocumented hardware starting here, something specfic to the 'W' series LC871 chips, which don't have a public data sheet. Guessing that this is a one-wire interface with some proprietary Sanyo/ONsemi format; I think it's the same one used by the TCB87-TypeC debug interface, but here it's being reused afaict mostly to generate the 750 kHz modulation pulses. Names here were gleaned from data files included with the toolthain. Has an interrupt that can fire after the receive ends, when we're ready for the ADC to begin. This seems to be vector 0023h 7 6 5 4 3 2 1 0 reg ---------------------------------------------------------------------------- EN TX CHGP IF IE FEB0h_WCON Control reg EN Overall enable bit for the whole peripheral TX Transmit enable CHGP Charge pump enable, turned off by hardware at RX start? IF Interrupt flag IE Interrupt enable SLO DRY OVL FEB1h_WMOD Mode bits SLO Slow / deprioritize the CPU until done with scan DRY Dry run; timers run, but no I/O happens OVL Overlap RX and TX, both phases end simultaneously Divisor, 8-bit. Fclk = Fosc / 2 / (1 + N) FEB2h_WCLKG Clock gen config Number of clock cycles to transmit for FEB3h_WSND Send counter, 8-bit Number of clocks to receive/integrate for FEB4h_WRCV Receive counter, 7-bit Wait time between receive and repeated send FEB5h_WWAI Wait counter, 7-bit (init to 32h) FEB6h_WCDLY0 Delay config? ack? flag? flag? flag? mode? mode? FEB7h_WCDLY1 Parallel word to latch out just before send FEB8h_WSADRL Parallel data word Modified in an unknown way during REPEAT transmit FEB9h_WSADRH Parallel word to latch out just before receive FEBAh_WRADRL Parallel data word FEBBh_WRADRH Relates to WRS6, WRS7, WRS9 (enables) FEBCh_WPMR0 Pin enable/mapping Relates to WRS4 (sel bit 1) FEBDh_WPMR1 Relates to P01 izero, P02 -Vpmp, P03 dir FEBEh_WPMR2 (unused except by factory test support) FEBFh_WPLLC PLL for higher freq? The word-wide ports WSADR and WRADR are both set (sometimes by writing twice, others by copying from WRADR to WSADR after writing WRADR) from model-specific tables of multiplexer control values. Marked in pins.txt as WRS.