Re: [TSCM-L] RSA compromise via the processor branch prediction module

From: coderman <code..._at_gmail.com>
Date: Tue, 21 Nov 2006 11:09:03 -0800

reason #43,756 to use a hardware crypto implementation[0]. reminds me
of the AES cache timing side channels[1]. (although to be fair, some
architectures can do these algorithms safely in software, just very
few[2]).

0. "VIA PadLock Security Engine"
  http://www.via.com.tw/en/initiatives/padlock/hardware.jsp

1. "Cache-timing attacks on AES"
  http://cr.yp.to/antiforgery/cachetiming-20041111.pdf

2. "Cell Broadband Engine Architecture"
  http://www-128.ibm.com/developerworks/power/library/pa-cellperf/

best regards,
Received on Sat Mar 02 2024 - 00:57:24 CST