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Expedition PCB - Pinnacle - Version 2013.0.543.380
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Job Directory:        S:\Projects\156-DDR4\DDR4x16_SI\Design\71-563300-A\PCB\

Design Status Report: S:\Projects\156-DDR4\DDR4x16_SI\Design\71-563300-A\PCB\LogFiles\DesignStatus_01.txt

Thu Jan 30 11:59:44 2014

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DESIGN STATUS
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Board Size Extents  ............ 16.5 X 18 (mm)
Route Border Extents  .......... 15.992 X 17.492 (mm)
Actual Board Area  ............. 297 (mm)
Actual Route Area  ............. 279.73206 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    594 Sq. (mm)      312.53413 Sq. (mm)52.62 %

Pins  .......................... 375
Pins per Route Area  ........... 1.34057 Pins/Sq. (mm)

Layers  ........................ 6
    Layer 1 is a signal layer
        Trace Widths  .......... 0.127
    Layer 2 is a Positive Plane Layer with nets
        VDD
        Trace Widths  .......... None.
    Layer 3 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 0.0762
    Layer 5 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 6 is a signal layer
        Trace Widths  .......... 0.127

Nets  .......................... 103
Connections  ................... 287
Open Connections  .............. 0
Differential Pairs  ............ 0
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (mm)
Netline Manhattan Length  ...... 0 (mm)
Total Trace Length  ............ 222.53612 (mm)

Trace Widths Used (mm)  ........ 0.0762, 0.127
Vias  .......................... 104
Via Span  Name                   Quantity
   1-6    Via 616th_Tented       104

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 137
    Parts Mounted on Top  ...... 92
        SMD  ................... 5
        Through  ............... 0
        Test Points  ........... 87
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 45
        SMD  ................... 45
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 191
    Holes per Board Area  ...... 0.6431 Holes/Sq. (mm)
Mounting Holes  ................ 0
