CES Diagnostics Report

Date: 2009-09-21 13:31:13

Log file: S:\Projects\92-GDDR5\Design\GDDR5_probe\CES\Output\PCB_Layout_Temp\gddr3\PGRAHAMPC\pgraham\CESDiagnostics_20090921_133112.html


Test: CES database initialization

Result: OK

Time: 0 seconds

Test: Constraint class name unique

Result: OK

Time: 0 seconds

Test: Clearance rule in all schemes

Result: OK

Time: 0 seconds

Test: Layer numbering

Result: OK

Time: 0 seconds

Test: Layer in all Z-axis clearance rules

Result: OK

Time: 0 seconds

Test: Victims and aggressors valid

Result: OK

Time: 0 seconds

Test: Component valid

Result: OK

Time: 0 seconds

Test: Pin in net and component

Result: OK

Time: 0 seconds

Test: Pin sets consistency

Result: OK

Time: 0 seconds

Test: Physical net unique

Result: OK

Time: 0 seconds

Test: Pin reference to net valid

Result: OK

Time: 0 seconds

Test: Electrical net unique

Result: OK

Time: 0 seconds

Test: Electrical net consistency

Result: OK

Time: 0 seconds

Test: Analog nets consistency

Result: OK

Time: 0 seconds

Test: All used constraint classes valid

Result: OK

Time: 0 seconds

Test: All used net classes valid

Result: OK

Time: 0 seconds

Test: Differential pair with two electrical nets

Result: OK

Time: 0 seconds

Test: Electrical nets belonging to differential pair assigned to the same net class

Result: OK

Time: 0 seconds

Test: Unique pin pairs in electrical net

Result: OK

Time: 0 seconds

Test: Connection pin pairs in electrical net

Result: OK

Time: 0 seconds

Test: Unique fromtos in physical net

Result: OK

Time: 0 seconds

Test: Fromto in only one net

Result: OK

Time: 0 seconds

Test: Constraints consistency

Result: OK

Time: 0 seconds

Test: Default objects

Result: OK

Time: 0 seconds

Test: Mapping of schematic and physical nets

Result: OK

Time: 0 seconds

Test: Reference designator vs. component name

Result: OK

Time: 0 seconds

Report summary:

Tests passed: 26

Tests with error(s): 0