
                               Forward Annotation
                               ------------------

                        03:42 PM Wednesday, June 13, 2012
         Job Name: S:\Projects\92-GDDR5\DDR4_new\Design\PCB\DDR4_new.pcb


Version:  01.01.00

     The PDBs listed in the project file will be searched to satisfy the parts
      requirements of the iCDB and to refresh with newer data any duplicates found in the
      Target PDB.

     The schematic source is a Common Data Base.

     The AllowAlphaRefDes status indicates that reference
      designators containing all alpha characters should be deleted
      and the relevant symbols repackaged.



     Common Data Base has been read

     Target PDB Name: Work\Layout_Temp\PartsDB.pdb

     Number of Part Numbers: 6
          Part Numb: BuriedR_100ohms_50persquare -> Vend Part: BuriedR_100ohms_50persquare 
          Part Numb: DDR4_78BGA_11x13_BOTTOM -> Vend Part: DDR4_78BGA_11x13_BOTTOM 
          Part Numb: DDR4_78BGA_11x13_TOP -> Vend Part: DDR4_78BGA_11x13_TOP 
          Part Numb: TEST_POINT_11x20dia_round -> Vend Part: TEST_POINT_11x20dia_round 
          Part Numb: TEST_POINT_11x20x30_TOP -> Vend Part: TEST_POINT_11x20x30_TOP 
          Part Numb: 09-000089 -> Vend Part: 09-000089 

     Number of Part Names: 0

     Number of Part Labels: 0


     Checking for value differences between symbol properties and PartsDB properties

     Checking the validity of the packaging of prepackaged schematic
      symbols.  Only the first error in symbols having the same
      Reference Designator will be reported.

     The packaging of all prepackaged schematic symbols is consistent
      with the Parts DataBase data for the cross mapping of
      symbol pin names to Part Number pin numbers.
      Symbols that were not prepackaged will now be packaged correctly.
      
     No errors in Existing Schematic Packaging.

     The Common DataBase has been read and will be packaged.
     Clustering 136 Symbols:
             136  ***********************************
             100  **************************************************
              50  **************************************************
     Clustering is Complete

     Packager Assignments successfully completed



     101 nets were found containing 341 pins
     136 components were found

     Creating a formatted Schematic Netlist (LogFiles\SchematicNetlist.txt)...
     A formatted Schematic Netlist has been created.

     The Logic DataBase has been compiled from the Schematic Design.
      Use Netload to bring the Component Design into sync.

     Logic Data has been successfully Compiled with no errors or warnings.
      Please proceed with your component Design.
                                     NetLoad
                                     -------

                        03:43 PM Wednesday, June 13, 2012
         Job Name: S:\Projects\92-GDDR5\DDR4_new\Design\PCB\DDR4_new.pcb


Version:  02.11.12

	Netloading the Layout.  Unused components will be deleted.

	Unconnected pins will be set to net "(Net0)".

	Schematic reference designator changes will be forward annotated.


     Netload completed successfully with 0 warning(s).
     
     Back Annotating...

  Updating Logic Database...

     Version:  99.00.05

     No changes made to Existing Schematic Packaging.


     There is no symbol data to be back annotated to the schematic source.


     The Logic DataBase has been updated and the Common DataBase has
      automatically been brought into sync with the Logic DataBase.
      Please proceed with your design.

     Finished updating the Logic Database.

     Creating a formatted Schematic Netlist (LogFiles\AfterBakAnnoNetlist.txt)...
     A formatted Schematic Netlist has been created.

     Creating a new netlist text file (LogFiles\KeyinNetList.txt)
      from the Logic Database (Work\Layout_Temp\LogicDB.lgc)...
  A new netlist text file has been generated.



                 Beginning Netload on the Layout Design.
           ---------------------------------------------------

Forward-Annotation on the Layout Design has been successfully completed.

There were 0 reassignments of nets.
There were 0 traces broken back.
There were 0 nets removed from the Layout Design.