Model
Description
Specification and Pod Chipset Web/Spec Info
Option for:
167xG, 16522A
and 16720A
Lead Set
10460A
TTL Clock Pod
Clock output type: 10H125 with 47 Ω series; true & inverted
Clock output rate: 100 MHz maximum
Clock out delay: 11 ns maximum in 9 steps
Clock input type: TTL – 10H124
Clock input rate: dc to 100 MHz
Pattern input type: TTL – 10H124 (no connect = logic 1)
Clock-in to clock-out: approximately 30 ns
Pattern-in to recognition: approximately 15 ns + 1 clk period
011
10498A
10461A
TTL Data Pod
Output type: 10H125 with 100 Ω series
Maximum clock: 200 MHz
Skew [1]: typical < 2 ns; worst case = 4 ns
014
10498A
10462A
3-State TTL/CMOS Data Pod
Output type: 74ACT11244 with 100 Ω series; 10H125 on non
3-state channel 7 [2]
3-state enable: negative true, 100 KΩ to GND, enabled
on no connect
Maximum clock: 100 MHz
Skew [1]: typical < 4 ns; worst case = 12 ns
http://focus.ti.com/lit/ds/symlink/sn74avc16244.pdf013
10498A
10463A
ECL Clock Pod
Clock output: type 10H116 differential unterminated; and
differential with 330 Ω to –5.2V and 47 Ω series
Clock output rate: 300 MHz maximum
Clock input type: ECL – 10H116 with 50 KΩ to –5.2v
Clock input rate: dc to 300 MHz
Pattern input type: ECL – 10H116 with 50 KΩ (no connect = logic 0)
Clock-in to clock-out: approximately 30 ns
Pattern-in to recognition: approximately 15 ns + 1 clk period
021
10498A
10464A
ECL Data Pod (terminated)
Output type: 10H115 with 330 Ω pulldown, 47 Ω series
Maximum clock: 300 MHz
Skew [1]: typical < 1 ns; worst case = 2 ns
022
10498A
10465A
ECL Data Pod (unterminated)
Output type: 10H115 (no termination)
Maximum clock: 300 MHz
Skew [1]: typical < 1 ns; worst case = 2 ns
023
10347A
10466A
Obsolete
Replaced by 10483A
3-State TTL/3.3 volt Data Pod
Output type: 74LVT244 with 100 Ω series; 10H125 on non
3-state channel 7 [2]
3-state enable: negative true, 100 KΩ to GND, enabled on no
connect
Maximum clock: 200 MHz
Skew [1]: typical < 3 ns; worst case = 7 ns
http://focus.ti.com/lit/ds/symlink/sn74avc16244.pdf012
10498A
10468A
5 volt PECL Clock Pod
Clock output type: 100EL90 (5V) with 348 Ω pulldown to
ground and 42 Ω in series
Clock output rate: 300 MHz maximum
Clock input type: 100EL91 PECL (5V), no termination
Clock input rate: dc to 300 MHz
Pattern input type: 100EL91 PECL (5V), no termination
(no connect = logic 0)
Clock-in to clock-out: approximately 30 ns
Pattern-in to recognition: approximately 15 ns + 1 clk period
031
10498A
10469A
5 volt PECL Data Pod
Clock Output type: 100EL90 (5V) with 348 Ω pulldown to
ground and 42 Ω in series
Maximum clock: 300 MHz
Skew [1]: typical < 500 ps; worst case = 1 ns
032
10498A
10470A
3.3 volt LVPECL Clock Pod
Clock output type: 100LVEL90 (3.3V) with 215 Ω pulldown
to ground and 42 Ω in series
Clock output rate: 300 MHz maximum
Clock input type: 100LVEL91 LVPECL (3.3V), no termination
Clock input rate: dc to 300 MHz
Pattern input type: 100LVEL91 LVPECL (3.3V), no termination
(no connect = logic 0)
Clock-in to clock-out: approximately 30 ns
Pattern-in to recognition: approximately 15 ns + 1 clk period
033
10498A
10471A
3.3 volt LVPECL Data Pod
Output type: 100LVEL90 (3.3V) with 215 Ω pull down to
ground and 42 Ω in series
Maximum clock: 300 MHz
Skew [1]: typical < 500 ps; worst case = 1 ns
034
10498A
10472A
2.5V CLOCK POD
Clock output type: 74AVC16244
Clock output rate: 200 MHz maximum
Clock out delay: approximately 8 ns total in 14 steps
Clock input type: 74AVC16244 (3.6V max)
Clock input rate: DC to 200 MHz
Pattern input type: 74AVC16244 (3.6V max; no connect = logic 0)
Clock in to clock out: approximately 30 ns
Pattern in to recognition: approximately 15 ns + 1 clock period
http://focus.ti.com/lit/ds/symlink/sn74avc16244.pdf015
10498A
10473A
3-STATE 2.5V DATA POD
Output type: 74AVC16244
3-State Enable: negative true; no connect = enabled
Maximum clock: 300 MHz
Skew [1]: Typical less than 1 ns, worst case 2 ns
http://focus.ti.com/lit/ds/symlink/sn74avc16244.pdf016
10498A
10475A
1.8V CLOCK POD
Clock output type: 74AVC16244
Clock output rate: 200 MHz maximum
Clock out delay: approximately 8 ns total in 14 steps
Clock input type: 74AVC16244 (3.6V max)
Clock input rate: DC to 200 MHz
Pattern input type: 74AVC16244 (3.6V max; no connect = logic 0)
Clock in to clock out: approximately 30 ns
Pattern in to recognition: approximately 15 ns + 1 clock period
http://focus.ti.com/lit/ds/symlink/sn74avc16244.pdf041
10498A
10476A
3-STATE 1.8V DATA POD
Output type: 74AVC16244
3-state enable: negative true; no connect = enabled
Maximum clock: 300 MHz
Skew [1]: Typical less than 1.5 ns, worst case 2.5 ns
http://focus.ti.com/lit/ds/symlink/sn74avc16244.pdf042
10498A
10477A
3.3V CLOCK POD
Clock output type: 74AVC16244
Clock output rate: 200 MHz maximum
Clock out delay: approximately 8 ns total in 14 steps
Clock input type: 74AVC16244 (3.6V max)
Clock input rate: DC to 200 MHz
Pattern input type: 74AVC16244 (3.6V max; no connect = logic 0)
Clock in to clock out: approximately 30 ns
Pattern in to recognition: approximately 15 ns + 1 clock period
http://focus.ti.com/lit/ds/symlink/sn74avc16244.pdf017
10498A
10483A
3-STATE 3.3V DATA POD
Output type: 74AVC16244
3-state enable: negative true; no connect = enabled
Maximum clock: 300 MHz
Skew [1]: Typical less than 1 ns, worst case 2 ns
http://focus.ti.com/lit/ds/symlink/sn74avc16244.pdf018
10498A
E8140A
LVDS CLOCK POD
Clock output type: 65LVDS179 (LVDS) and 10H125 (TTL)
Clock output rate: 200 MHz maximum (LVDS and TTL)
Clock out delay: approximately 8 ns total in 14 steps
Clock input type: 65LVDS179 (LVDS with 100 Ω)
Clock input rate: DC to 150 MHz (LVDS)
Pattern input type: 10H124 (TTL) (no connect = logic 1)
Clock in to clock out: approximately 30 ns
Pattern in to recognition: approximately 15 ns + 1 clock period
http://www-s.ti.com/sc/psheets/slls301i/slls301i.pdf051
E8142A
E8141A
LVDS DATA POD
Output type: 65LVDS389 (LVDS data lines)
3-state enable: positive true; no connect = enabled
Maximum clock: 300 MHz
Skew [1]: Typical less than 1 ns, worst case 2 ns
http://focus.ti.com/lit/ds/symlink/sn74avc16244.pdf052
E8142A