Result Details:

Result Details
Worst VIH(See image)NumOfMeas2.000PUTCA0PUT SrcChannel 4Supporting PinN/ASupporting Pin SrcN/APassLimit Min (VrefCA_Volt+AcLevels_CA_Volt)750.000000000mV

Trial 1

Trial 1: Worst VIH

VIH.CA(DC) Reference: JEDEC Standard No. 79-3E, Table 23 (Vref=0.75; VDD=1.50)

Test Summary: FAIL Test Description: DC Input Logic High
Pass Limits:[VrefCA_Volt+DcLevels_VoltV to VDDCA_VoltV]VIH.CA(DC)1.245490000000V

Result Details:

Result Details
Worst VIH(See image)NumOfMeas2.000PUTCA0PUT SrcChannel 4Supporting PinN/ASupporting Pin SrcN/APassLimit Min (VrefCA_Volt+DcLevels_Volt)700.000000000mVPassLimit Max (VDDCA_Volt)1.200000000000V

Trial 1

Trial 1: Worst VIH

VIL.CA(AC) Reference: JEDEC Standard No. 79-3E, Table 23 (Vref=0.75)

Test Summary: Pass Test Description: AC Input Logic Low
Pass Limits:<= VrefCA_Volt-AcLevels_CA_VoltVVIL.CA(AC)-19.240000000mV

Result Details:

Result Details
Worst VIL(See image)NumOfMeas2.000PUTCA0PUT SrcChannel 4Supporting PinN/ASupporting Pin SrcN/APassLimit Max (VrefCA_Volt-AcLevels_CA_Volt)450.000000000mV

Trial 1

Trial 1: Worst VIL

VIL.CA(DC) Reference: JEDEC Standard No. 79-3E, Table 23 (Vref=0.75; VSS=0.00)

Test Summary: FAIL Test Description: DC Input Logic Low
Pass Limits:[0.000000000000V to VrefCA_Volt-DcLevels_VoltV]VIL.CA(DC)-19.240000000mV

Result Details:

Result Details
Worst VIL(See image)NumOfMeas2.000PUTCA0PUT SrcChannel 4Supporting PinN/ASupporting Pin SrcN/APassLimit Max (VrefCA_Volt-DcLevels_Volt)500.000000000mV

Trial 1

Trial 1: Worst VIL

VIH.DQ(AC) Reference: JEDEC Standard No. 79-3E, Table 24 (Vref=0.75)

Test Summary: Pass Test Description: AC Input Logic High
Pass Limits:>= VrefDQ_Volt+AcLevels_DQ_VoltVVIH.DQ(AC)967.608300000mV

Result Details:

Result Details
Worst VIH(See image)Number of burst(s) measured1NumOfMeas1.000PUTDQ0PUT SrcChannel 3Supporting PinDQS0_t,DQS0_cSupporting Pin SrcChannel 2Chip Select Pin SourceN/APassLimit Min (VrefDQ_Volt+AcLevels_DQ_Volt)750.000000000mV

Trial 1

Trial 1: Worst VIH

VIH.DQ(DC) Reference: JEDEC Standard No. 79-3E, Table 24 (Vref=0.75; VDD=1.50)

Test Summary: Pass Test Description: DC Input Logic High
Pass Limits:[VrefDQ_Volt+DcLevels_VoltV to VDDQ_VoltV]VIH.DQ(DC)967.608300000mV

Result Details:

Trial 1

Trial 1: Worst VIH

VIL.DQ(AC) Reference: JEDEC Standard No. 79-3E, Table 24 (Vref=0.75)

Test Summary: Pass Test Description: AC Input Logic Low
Pass Limits:<= VrefDQ_Volt-AcLevels_DQ_VoltVVIL.DQ(AC)428.115800000mV

Result Details:

Result Details
Worst VIL(See image)Number of burst(s) measured1NumOfMeas1.000PUTDQ0PUT SrcChannel 3Supporting PinDQS0_t,DQS0_cSupporting Pin SrcChannel 2Chip Select Pin SourceN/APassLimit Max (VrefDQ_Volt-AcLevels_DQ_Volt)450.000000000mV

Trial 1

Trial 1: Worst VIL

VIL.DQ(DC) Reference: JEDEC Standard No. 79-3E, Table 24 (Vref=0.75; VSS=0.00)

Test Summary: Pass Test Description: DC Input Logic Low
Pass Limits:[0.000000000000V to VrefDQ_Volt-DcLevels_VoltV]VIL.DQ(DC)428.115800000mV

Result Details:

Trial 1

Trial 1: Worst VIL

VSEH(Strobe) Reference: JEDEC Standard No. 79-3E, Table 27 (VDDQ=1.2)

Test Summary: Pass Test Description: Single-ended High Level Voltage for Strobes
Pass Limits:>= VDDQ_Volt/2 + 0.220VVSEH845.571000000mV

Result Details:

Result Details
Worst VSEH(See image)Number of burst(s) measured1NumOfMeas4.000Min8.455710e-001Max1.023825e+000PUTDQS0_t,GndPUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/APassLimit Min (VDDQ_Volt/2 + 0.220)820.000000000mV

Trial 1

Trial 1: Worst VSEH

VSEL(Strobe) Reference: JEDEC Standard No. 79-3E, Table 27 (VDDQ=1.2)

Test Summary: Pass Test Description: Single-ended Low Level Voltage for Strobes
Pass Limits:<= VDDQ_Volt/2 - 0.220VVSEL-1.224207000000V

Result Details:

Result Details
Worst VSEL(See image)Number of burst(s) measured1NumOfMeas3.000Min-1.276162e+000Max-1.224207e+000PUTDQS0_t,GndPUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/APassLimit Max (VDDQ_Volt/2 - 0.220)380.000000000mV

Trial 1

Trial 1: Worst VSEL

VSEH(Clock) Reference: JEDEC Standard No. 79-3E, Table 27 (VDDQ=1.5)

Test Summary: Pass Test Description: Single-ended High Level Voltage
Pass Limits:>= VDDCA_Volt/2 + 0.220VVSEH(AC)1.056850000000V

Result Details:

Result Details
Worst VSEH(See image)NumOfMeas10.000Min1.056850e+000Max1.088420e+000PUTCK_t,GndPUT SrcChannel 1PassLimit Min (VDDCA_Volt/2 + 0.220)820.000000000mV

Trial 1

Trial 1: Worst VSEH

VSEL(Clock) Reference: JEDEC Standard No. 79-3E, Table 27 (VDDQ=1.5)

Test Summary: Pass Test Description: Single-ended Low Level Voltage
Pass Limits:<= VDDCA_Volt/2 - 0.220VVSEL-1.097450000000V

Result Details:

Result Details
Worst VSEL(See image)NumOfMeas10.000Min-1.149930e+000Max-1.097450e+000PUTCK_t,GndPUT SrcChannel 1PassLimit Max (VDDCA_Volt/2 - 0.220)380.000000000mV

Trial 1

Trial 1: Worst VSEL

VOH(AC) Reference: JEDEC Standard No. 79-3E, Table 30 (VTT=0.75; VDDQ=1.50)

Test Summary: Pass Test Description: AC Output Logic High
Pass Limits:>= VrefDQ_Volt+0.12VVOH(AC)1.199150000000V

Result Details:

Result Details
Worst VOH(See image)NumOfMeas2.000PUTDQ0,GndPUT SrcChannel 3Supporting PinDQS0_t,DQS0_cSupporting Pin SrcChannel 2Chip Select Pin SourceN/APassLimit Min (VrefDQ_Volt+0.12)720.000000000mV

Trial 1

Trial 1: Worst VOH

VOH(DC) Reference: JEDEC Standard No. 79-3E, Table 30 (VDDQ=1.50)

Test Summary: Pass Test Description: DC Output Logic High
Pass Limits:>= 0.9*VDDQ_VoltVVOH(DC)1.199150000000V

Result Details:

Trial 1

Trial 1: Worst VOH

VOL(AC) Reference: JEDEC Standard No. 79-3E, Table 30 (VTT=0.75; VDDQ=1.50)

Test Summary: Pass Test Description: AC Output Logic Low
Pass Limits:<= VrefDQ_Volt-0.12VVOL(AC)-40.670000000mV

Result Details:

Result Details
Worst VOL(See image)NumOfMeas2.000PUTDQ0,GndPUT SrcChannel 3Supporting PinDQS0_t,DQS0_cSupporting Pin SrcChannel 2Chip Select Pin SourceN/APassLimit Max (VrefDQ_Volt-0.12)480.000000000mV

Trial 1

Trial 1: Worst VOL

VOL(DC) Reference: JEDEC Standard No. 79-3E, Table 30 (VDDQ=1.50)

Test Summary: Pass Test Description: DC Output Logic Low
Pass Limits:<= 0.1*VDDQ_VoltVVOL(DC)-40.670000000mV

Result Details:

Trial 1

Trial 1: Worst VOL

SRQseR Reference: JEDEC Standard No. 79-3E, Table 33

Test Summary: FAIL Test Description: Output signal minimum rising slew rate
Pass Limits:[2.000000000000V/ns to 4.000000000000V/ns]SRQseR8.413856000000V/ns

Result Details:

Result Details
Worst SRQseR(See image)Number of burst(s) measured1NumOfMeas2.000SRQSeR_time29psVref600mVVoh_ac720mVVol_ac480mVPUTDQ0,GndPUT SrcChannel 3Supporting PinDQS0_t,DQS0_cSupporting Pin SrcChannel 2Chip Select Pin SourceN/A

Trial 1

Trial 1: Worst SRQseR

SRQseF Reference: JEDEC Standard No. 79-3E, Table 33

Test Summary: FAIL Test Description: Output signal minimum falling slew rate
Pass Limits:[2.000000000000V/ns to 4.000000000000V/ns]SRQseF914.063300000mV/ns

Result Details:

Result Details
Worst SRQseF(See image)Number of burst(s) measured1NumOfMeas1.000SRQSeF_time263psVref600mVVoh_ac720mVVol_ac480mVPUTDQ0,GndPUT SrcChannel 3Supporting PinDQS0_t,DQS0_cSupporting Pin SrcChannel 2Chip Select Pin SourceN/A

Trial 1

Trial 1: Worst SRQseF

Overshoot amplitude (Address, Control, Clock, Chip Select, Clock Enable) Reference:

Test Summary: Pass Test Description: Peak amplitude of AC overshoot
Pass Limits:<= 350.000000000mVOvershoot amplitude (Address, Control, Clock, Chip Select, Clock Enable)106.020000000mV

Result Details:

Result Details
Overshoot Width100.500700nsOvershoot Reference1.200VPUTCA0PUT SrcChannel 4Overshoot Amplitude(See image)

Trial 1

Trial 1: Overshoot Amplitude

Overshoot area (Address, Control, Clock, Chip Select, Clock Enable) Reference:

Test Summary: FAIL Test Description: OverShoot area above VDDCA
Pass Limits:<= 100.000000000mV-nsOvershoot Area (Address, Control, Clock, Chip Select, Clock Enable)5.327542000000V-ns

Result Details:

Result Details
Overshoot amplitude106mVOvershoot Width100.500700nsOvershoot Reference1.200VPUTCA0PUT SrcChannel 4Overshoot Area(See image)

Trial 1

Trial 1: Overshoot Area

Undershoot amplitude (Address, Control, Clock, Chip Select, Clock Enable) Reference:

Test Summary: Pass Test Description: Peak amplitude of AC undershoot
Pass Limits:<= 350.000000000mVUndershoot amplitude (Address, Control, Clock, Chip Select, Clock Enable)151.420000000mV

Result Details:

Result Details
Undershoot Width536.372psUndershoot Reference0.000VPUTCA0PUT SrcChannel 4Undershoot Amplitude(See image)

Trial 1

Trial 1: Undershoot Amplitude

Undershoot area (Address, Control, Clock, Chip Select, Clock Enable) Reference:

Test Summary: Pass Test Description: UnderShoot area below VSS
Pass Limits:<= 100.000000000mV-nsUndershoot Area (Address, Control, Clock, Chip Select, Clock Enable)40.608730000mV-ns

Result Details:

Result Details
Undershoot Amplitude151mVUndershoot Width536.372psUndershoot Reference0.000VPUTCA0PUT SrcChannel 4Undershoot Area(See image)

Trial 1

Trial 1: Undershoot Area

Overshoot amplitude (Data, Strobe, Mask) Reference:

Test Summary: Pass Test Description: Peak amplitude of AC overshoot
Pass Limits:<= 350.000000000mVOvershoot amplitude (Data, Strobe, Mask)111.160000000mV

Result Details:

Result Details
Overshoot Width690.642psOvershoot Reference1.200VPUTDQ0PUT SrcChannel 3Overshoot Amplitude(See image)

Trial 1

Trial 1: Overshoot Amplitude

Overshoot area (Data, Strobe, Mask) Reference:

Test Summary: Pass Test Description: OverShoot area above VDDQ
Pass Limits:<= 100.000000000mV-nsOvershoot Area (Address, Control, Clock, Chip Select, Clock Enable)38.385880000mV-ns

Result Details:

Result Details
Overshoot amplitude111mVOvershoot Width690.642psOvershoot Reference1.200VPUTDQ0PUT SrcChannel 3Overshoot Area(See image)

Trial 1

Trial 1: Overshoot Area

Undershoot amplitude (Data, Strobe, Mask) Reference:

Test Summary: Pass Test Description: Peak amplitude of AC undershoot
Pass Limits:<= 350.000000000mVUndershoot amplitude (Data, Strobe, Mask)122.010000000mV

Result Details:

Result Details
Undershoot Width206.618psUndershoot Reference0.000VPUTDQ0PUT SrcChannel 3Undershoot Amplitude(See image)

Trial 1

Trial 1: Undershoot Amplitude

Undershoot area (Data, Strobe, Mask) Reference:

Test Summary: Pass Test Description: UnderShoot area below VSS
Pass Limits:<= 100.000000000mV-nsUndershoot Area (Data, Strobe, Mask)12.604710000mV-ns

Result Details:

Result Details
Undershoot Amplitude122mVUndershoot Width206.618psUndershoot Reference0.000VPUTDQ0PUT SrcChannel 3Undershoot Area(See image)

Trial 1

Trial 1: Undershoot Area

VIHdiff.CK(AC) Reference: JEDEC Standard No. 79-3E, Table 25

Test Summary: Pass Test Description: Differential AC Input Logic High Voltage
Pass Limits:>= 2*(VIHAC_CA_Volt-VrefCA_Volt)VVIHdiff(AC)1.022890000000V

Result Details:

Result Details
Worst VIH(See image)NumOfMeas10.000Min1.022890e+000Max1.078060e+000PUTCLK_t,CLK_cPUT SrcChannel 1PassLimit Min (2*(VIHAC_CA_Volt-VrefCA_Volt))300.000000000mV

Trial 1

Trial 1: Worst VIH

VIHdiff.CK(DC) Reference: JEDEC Standard No. 79-3E, Table 25

Test Summary: Pass Test Description: Differential DC Input Logic High Voltage
Pass Limits:>= 2*(VIHDC_CA_Volt-VrefCA_Volt)VVIHdiff(DC)1.022890000000V

Result Details:

Result Details
Worst VIH(See image)NumOfMeas10.000Min1.022890e+000Max1.078060e+000PUTCLK_t,CLK_cPUT SrcChannel 1PassLimit Min (2*(VIHDC_CA_Volt-VrefCA_Volt))200.000000000mV

Trial 1

Trial 1: Worst VIH

VILdiff.CK(AC) Reference: JEDEC Standard No. 79-3E, Table 25

Test Summary: Pass Test Description: Differential AC Input Logic Low Voltage
Pass Limits:<= 2*(VILAC_CA_Volt-VrefCA_Volt)VVILdiff(AC)-1.075080000000V

Result Details:

Result Details
Worst VIL(See image)NumOfMeas10.000Min-1.159720e+000Max-1.075080e+000PUTCLK_t,CLK_cPUT SrcChannel 1PassLimit Max (2*(VILAC_CA_Volt-VrefCA_Volt))-300.000000000mV

Trial 1

Trial 1: Worst VIL

VILdiff.CK(DC) Reference: JEDEC Standard No. 79-3E, Table 25

Test Summary: Pass Test Description: Differential DC Input Logic Low Voltage
Pass Limits:<= 2*(VILDC_CA_Volt-VrefCA_Volt)VVILdiff(DC)-1.075080000000V

Result Details:

Result Details
Worst VIL(See image)NumOfMeas10.000Min-1.159720e+000Max-1.075080e+000PUTCLK_t,CLK_cPUT SrcChannel 1PassLimit Max (2*(VILDC_CA_Volt-VrefCA_Volt))-200.000000000mV

Trial 1

Trial 1: Worst VIL

VIHdiff.DQS(AC) Reference: JEDEC Standard No. 79-3E, Table 25

Test Summary: Pass Test Description: Differential AC Input Logic High Voltage
Pass Limits:>= 2*(VIHAC_DQ_Volt-VrefDQ_Volt)VVIHdiff(AC)681.500000000mV

Result Details:

Result Details
Worst VIHDiff(See image)NumOfMeas5.000Min6.815000e-001Max1.027600e+000PUTDQS0_t,DQS0_cPUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/APassLimit Min (2*(VIHAC_DQ_Volt-VrefDQ_Volt))300.000000000mV

Trial 1

Trial 1: Worst VIHDiff

VIHdiff.DQS(DC) Reference: JEDEC Standard No. 79-3E, Table 25

Test Summary: Pass Test Description: Differential DC Input Logic High Voltage
Pass Limits:>= 2*(VIHDC_DQ_Volt-VrefDQ_Volt)VVIHdiff(DC)681.500000000mV

Result Details:

Trial 1

Trial 1: Worst VIHDiff

VILdiff.DQS(AC) Reference: JEDEC Standard No. 79-3E, Table 25

Test Summary: Pass Test Description: Differential AC Input Logic Low Voltage
Pass Limits:<= 2*(VILAC_DQ_Volt-VrefDQ_Volt)VVILdiff(AC)-1.073100000000V

Result Details:

Result Details
Worst VILDiff(See image)NumOfMeas4.000Min-1.280300e+000Max-1.073100e+000PUTDQS0_t,DQS0_cPUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/APassLimit Max (2*(VILAC_DQ_Volt-VrefDQ_Volt))-300.000000000mV

Trial 1

Trial 1: Worst VILDiff

VILdiff.DQS(DC) Reference: JEDEC Standard No. 79-3E, Table 25

Test Summary: Pass Test Description: Differential DC Input Logic Low Voltage
Pass Limits:<= 2*(VILDC_DQ_Volt-VrefDQ_Volt)VVILdiff(DC)-1.073100000000V

Result Details:

Trial 1

Trial 1: Worst VILDiff

VOHdiff(AC) Reference: JEDEC Standard No. 79-3E, Table 31(VDDQ=1.50)

Test Summary: Pass Test Description: Differential AC Output Logic High Voltage
Pass Limits:>= 0.2*VDDQ_VoltVVOHdiff(AC)711.800000000mV

Result Details:

Result Details
Worst VOHDiff(See image)NumOfMeas4.000Min7.118000e-001Max8.807000e-001PUTDQS0_t,DQS0_cPUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/APassLimit Min (0.2*VDDQ_Volt)240.000000000mV

Trial 1

Trial 1: Worst VOHDiff

VOLdiff(AC) Reference: JEDEC Standard No. 79-3E, Table 31(VDDQ=1.50)

Test Summary: Pass Test Description: Differential AC Output Logic Low Voltage
Pass Limits:<= -0.2*VDDQ_VoltVVOLdiff(AC)-1.119400000000V

Result Details:

Result Details
Worst VOLDiff(See image)NumOfMeas3.000Min-1.154000e+000Max-1.119400e+000PUTDQS0_t,DQS0_cPUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/APassLimit Max (-0.2*VDDQ_Volt)-240.000000000mV

Trial 1

Trial 1: Worst VOLDiff

SRQdiffR Reference: JEDEC Standard No. 79-3E, Table 35

Test Summary: FAIL Test Description: Differential Output Rising Slew Rate
Pass Limits:[4.000000000000V/ns to 8.000000000000V/ns]SRQdiffR2.122339000000V/ns

Result Details:

Result Details
Worst SRQdiffR(See image)Number of burst(s) measured1NumOfMeas4.000SRQdiffR_time226psMin2.122339000000V/nsMax4.749336000000V/nsVOHdiff_ac240mVVOLdiff_ac-240mVPUTDQS0_t,DQS0_cPUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/A

Trial 1

Trial 1: Worst SRQdiffR

SRQdiffF Reference: JEDEC Standard No. 79-3E, Table 35

Test Summary: FAIL Test Description: Differential Output Falling Slew Rate
Pass Limits:[4.000000000000V/ns to 8.000000000000V/ns]SRQdiffF2.222282000000V/ns

Result Details:

Result Details
Worst SRQdiffF(See image)Number of burst(s) measured1NumOfMeas4.000SRQdiffF_time216psMin2.222282000000V/nsMax2.417934000000V/nsVOHdiff_ac240mVVOLdiff_ac-240mVPUTDQS0_t,DQS0_cPUT SrcChannel 2Supporting PinDQ0Supporting Pin SrcChannel 3Chip Select Pin SourceN/A

Trial 1

Trial 1: Worst SRQdiffF

tDS(base) Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: DQ and DM input setup time - Differential
Pass Limits:>= tDS_Limit_minstDS81ps

Result Details:

Result Details
Worst tDS(See image)Number of burst(s) measured1.000000e+000NumOfMeas2.000PassLimit Min (tDS_Limit_min)75psCH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min81psMax141psMean111psStdev42ps

Trial 1

Trial 1: Worst tDS

tDH(base) Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: DQ and DM input hold time - Differential
Pass Limits:>= tDH_Limit_minstDH239ps

Result Details:

Result Details
Worst tDH(See image)Number of burst(s) measured1.000000e+000NumOfMeas2.000PassLimit Min (tDH_Limit_min)100psCH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min239psMax253psMean246psStdev10ps

Trial 1

Trial 1: Worst tDH

tDS-Diff(derate) Reference: JEDEC Standard No. 79-3E, Table 76,Table 77 and Table 78

Test Summary: Pass Test Description: DQ and DM input setup time - Differential
Pass Limits:>= tDSDiff_DeratedLimit_MinstDS81ps

Result Details:

Result Details
Worst tDSDiffDerate(See image)Mean Slewrate for DQ signal1.886380000000V/nsMean Slewrate for DQS signal4.853719000000V/nsBase limit value7.500000e-011Derated limit value-5.68101212884902E-12Number of burst(s) measured1.000000e+000NumOfMeas2.000PassLimit Min (tDSDiff_DeratedLimit_Min)69psDerated Limit MethodNominal methodCH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min81psMax141psMean111psStdev42ps

Trial 1

Trial 1: Worst tDSDiffDerate

tDH-Diff(derate) Reference: JEDEC Standard No. 79-3C, Table 76,Table 77 and Table 78

Test Summary: Pass Test Description: DQ and DM input hold time - Differential
Pass Limits:>= tDHDiff_DeratedLimit_MinstDH239ps

Result Details:

Result Details
Worst tDHDiffDerate(See image)Mean Slewrate for DQ signal1.670974000000V/nsMean Slewrate for DQS signal2.572725000000V/nsBase limit value1.000000e-010Derated limit value-1.11868920677163E-11Number of burst(s) measured1.000000e+000NumOfMeas2.000PassLimit Min (tDHDiff_DeratedLimit_Min)89psDerated Limit MethodNominal methodCH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min239psMax253psMean246psStdev10ps

Trial 1

Trial 1: Worst tDHDiffDerate

tDIPW Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: DQ and DM input pulse width
Pass Limits:>= 438pstDIPW1.217ns

Result Details:

Result Details
Worst tDIPW(See image)Number of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min1.217nsMax1.217nsMean1.217nsStdev0.000000000000s

Trial 1

Trial 1: Worst tDIPW

tVAC(Data) Reference: N/A

Test Summary: Pass Test Description: tVAC(Data)
Pass Limits:>= 35.0pstVAC(Data)1.0647ns

Result Details:

Result Details
WorsttVAC_DQ(See image)Number of burst(s) measured1NumOfMeas1.000NotePlease refer to the JEDEC specification for actual limit.Nominal Slew Rate2.738759e+000V/nsCH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseVIH(AC)(no value)VIL(AC)(no value)Sampling Points(no value)Min1.065nsMax1.065nsMean1.065nsStdev0.000000000000s

Trial 1

Trial 1: WorsttVAC_DQ

tWPRE Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: FAIL Test Description: Write preamble
Pass Limits:>= 800.000000000mtCKtWPRE799.523500000mtCK

Result Details:

Result Details
tWPRE(See image)tWPRE(s)999psNumber of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min799.523500000mtCKMax799.523500000mtCKMean799.523500000mtCKStdev0.000000000000tCK

Trial 1

Trial 1: tWPRE

tWPST Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: Write postamble
Pass Limits:>= 400.0000000000mtCKtWPST7.2000000000000E45tCK

Result Details:

Result Details
tWPST(See image)tWPST(s)9.0000000000000E36sNumber of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min7.2000000000000E45tCKMax7.2000000000000E45tCKMean7.2000000000000E45tCKStdev0.000000000000tCK

Trial 1

Trial 1: tWPST

tDQSS Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: DQS latching transition to associated clock edge
Pass Limits:[750.000000000mtCK to 1.250000000000tCK]tDQSS1.090405000000tCK

Result Details:

Result Details
Worst tDQSS_DDR3(See image)tDQSS(s)1.363nsNumber of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min1.090405000000tCKMax1.090405000000tCKMean1.090405000000tCKStdev0.000000000000tCK

Trial 1

Trial 1: Worst tDQSS_DDR3

tDSS Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: DQS falling edge to CK setup time
Pass Limits:>= 200.000000000mtCKtDSS536.118900000mtCK

Result Details:

Result Details
Worst tDSS(See image)tDSS(s)670psNumber of burst(s) measured1.000000e+000NumOfMeas5.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min536.118900000mtCKMax620.725900000mtCKMean569.116900000mtCKStdev31.778920000mtCK

Trial 1

Trial 1: Worst tDSS

tDSH Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: DQS falling edge hold time from CK
Pass Limits:>= 200.000000000mtCKtDSH379.972700000mtCK

Result Details:

Result Details
Worst tDSH(See image)tDSH(s)475psNumber of burst(s) measured1.000000e+000NumOfMeas5.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min379.972700000mtCKMax484.088300000mtCKMean433.808800000mtCKStdev40.412860000mtCK

Trial 1

Trial 1: Worst tDSH

tDQSL Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: DQS input low pulse width
Pass Limits:>= 400.000000000mtCKtDQSL524.042900000mtCK

Result Details:

Result Details
Worst tDQSL(See image)tDQSL(s)655psNumber of burst(s) measured1.000000e+000NumOfMeas4.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min524.042900000mtCKMax566.657500000mtCKMean539.459800000mtCKStdev18.784750000mtCK

Trial 1

Trial 1: Worst tDQSL

tDQSH Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: FAIL Test Description: DQS input high pulse width
Pass Limits:>= 400.000000000mtCKtDQSH398.635500000mtCK

Result Details:

Result Details
Worst tDQSH(See image)tDQSH(s)498psNumber of burst(s) measured1.000000e+000NumOfMeas5.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min398.635500000mtCKMax446.101500000mtCKMean430.122100000mtCKStdev19.195250000mtCK

Trial 1

Trial 1: Worst tDQSH

tIS(base) Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: Address and control input setup time
Pass Limits:>= tIS_Limit_minstIS254.2ps

Result Details:

Result Details
Worst tIS(See image)NumOfMeas3.000CH1_PUTSupporting PinCH1_SrcCK_t,CK_cCH2_PUTPlease select a signalCH2_SrcNot In UseCH3_PUTPlease select a signalCH3_SrcNot In UseCH4_PUTPin Under TestCH4_SrcCS_n,GndClocking Method1T TimingEdge TypeBOTH Rising and Falling edgePassLimit Min (tIS_Limit_min)75.0ps

Trial 1

Trial 1: Worst tIS

tIH(base) Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: Address and control input hold time
Pass Limits:>= tIH_Limit_minstIH330.9ps

Result Details:

Result Details
Worst tIH(See image)NumOfMeas3.000CH1_PUTSupporting PinCH1_SrcCK_t,CK_cCH2_PUTPlease select a signalCH2_SrcNot In UseCH3_PUTPlease select a signalCH3_SrcNot In UseCH4_PUTPin Under TestCH4_SrcCS_n,GndEdge TypeBOTH Rising and Falling edgePassLimit Min (tIH_Limit_min)100.0ps

Trial 1

Trial 1: Worst tIH

tIS(derate) Reference: JEDEC Standard No. 79-3E, Table 70, Table 71 and Table 72

Test Summary: Pass Test Description: Address and control input setup time
Pass Limits:>= tIS_DeratedLimit_MinstIS254.2ps

Result Details:

Result Details
Worst tISDerate(See image)NumOfMeas3.000Mean Slewrate for CA signal3.332165000000V/nsMean Slewrate for CLK signal6.188001000000V/nsBase limit value7.500000e-011Derated limit value2.96503055452044E-11CH1_PUTSupporting PinCH1_SrcCK_t,CK_cCH2_PUTPlease select a signalCH2_SrcNot In UseCH3_PUTPlease select a signalCH3_SrcNot In UseCH4_PUTPin Under TestCH4_SrcCS_n,GndClocking Method1T TimingEdge TypeBOTH Rising and Falling edgePassLimit Min (tIS_DeratedLimit_Min)104.7ps

Trial 1

Trial 1: Worst tISDerate

tIH(derate) Reference: JEDEC Standard No. 79-3E, Table 70, Table 71 and Table 72

Test Summary: Pass Test Description: Address and control input hold time
Pass Limits:>= tIH_DeratedLimit_MinstIH330.9ps

Result Details:

Result Details
Worst tIHDerate(See image)NumOfMeas3.000Mean Slewrate for CA signal2.680045000000V/nsMean Slewrate for CLK signal6.411065000000V/nsBase limit value1.000000e-010Derated limit value1.25206280041735E-11CH1_PUTSupporting PinCH1_SrcCK_t,CK_cCH2_PUTPlease select a signalCH2_SrcNot In UseCH3_PUTPlease select a signalCH3_SrcNot In UseCH4_PUTPin Under TestCH4_SrcCS_n,GndEdge TypeBOTH Rising and Falling edgePassLimit Min (tIH_DeratedLimit_Min)112.5ps

Trial 1

Trial 1: Worst tIHDerate

tVAC(CS,CA) Reference: N/A

Test Summary: Pass Test Description: tVAC(CS,CA)
Pass Limits:>= 35.0pstVAC(CS,CA)19.9914ns

Result Details:

Result Details
WorsttVAC_CS_CA(See image)NotePlease refer to the JEDEC specification for actual limit.Min1.999142e-008sMax1.850042e-007sNumOfMeas2.000000e+000Nominal Slew Rate3.546901e+000V/nsCH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseVIH(AC)0.75VIL(AC)0.45Sampling Points2000000

Trial 1

Trial 1: WorsttVAC_CS_CA

tIPWCS Reference: JEDEC Standard No. 209-3, Table 118

Test Summary: Pass Test Description: tIPWCS
Pass Limits:>= 700.000000000mtCKtIPWCS967.917100000mtCK

Result Details:

Result Details
WorsttIPWCS(See image)Min1.209896e-009sMax2.532630e-006sNo Of Edge1.000000e+001CH1_PUTSupporting PinCH1_SrcCK_t,CK_cCH2_PUTPlease select a signalCH2_SrcNot In UseCH3_PUTPlease select a signalCH3_SrcNot In UseCH4_PUTPin Under TestCH4_SrcCS_n,Gnd

Trial 1

Trial 1: WorsttIPWCS

tDQSQ Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: FAIL Test Description: DQS-DQ skew for DQS and associated DQ signals
Pass Limits:<= 135pstDQSQ211ps

Result Details:

Result Details
Worst tDQSQ(See image)Number of burst(s) measured1.000000e+000NumOfMeas3.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min-139psMax211psMean21psStdev177ps

Trial 1

Trial 1: Worst tDQSQ

tQH Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: FAIL Test Description: DQ/DQS output hold time from DQS
Pass Limits:>= 450.000000000mtCKtQH381.738100000mtCK

Result Details:

Result Details
Worst tQH(See image)Number of burst(s) measured1.000000e+000NumOfMeas3.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min381.738100000mtCKMax573.660500000mtCKMean446.875500000mtCKStdev109.812900000mtCK

Trial 1

Trial 1: Worst tQH

tLZDQ Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: DQ low-impedance time from CK,/CK
Pass Limits:>= 2.2000nstLZDQ3.6663ns

Result Details:

Result Details
tLZDQ(See image)Number of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UsetDQSCK Delay (cycle)3Sampling Points (Pts)2000000Min3.6663nsMax3.6663nsMean3.6663nsStdev0.0000000000000s

Trial 1

Trial 1: tLZDQ

tHZDQ Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: DQ out high-impedance time from CK,/CK
Pass Limits:<= 5.6890nstHZDQ4.4328ns

Result Details:

Result Details
tHZDQ(See image)Number of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_Src3tDQSCK Delay (cycle)Not In UseSampling Points (Pts)2000000Min4.4328nsMax4.4328nsMean4.4328nsStdev0.0000000000000s

Trial 1

Trial 1: tHZDQ

tRPRE Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: Read preamble
Pass Limits:>= 900.000000000mtCKtRPRE1.338093000000tCK

Result Details:

Result Details
tRPRE(See image)tRPRE(s)1.673nsNumber of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min1.338093000000tCKMax1.338093000000tCKMean1.338093000000tCKStdev0.000000000000tCK

Trial 1

Trial 1: tRPRE

tRPST Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: FAIL Test Description: Read postamble
Pass Limits:>= 300.0000000000mtCKtRPST277.8743000000mtCK

Result Details:

Result Details
tRPST(See image)tRPST(s)347psNumber of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min277.874300000mtCKMax277.874300000mtCKMean277.874300000mtCKStdev0.000000000000tCK

Trial 1

Trial 1: tRPST

tDQSCK Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: DQS output access time from CK,/CK
Pass Limits:[2.500ns to 5.500ns]tDQSCK4.143ns

Result Details:

Result Details
WorsttDQSCK(See image)Number of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UsetDQSCK Delay (cycle)3Sampling Points (Pts)2000000Min4.143nsMax4.143nsMean4.143nsStdev0.000000000000s

Trial 1

Trial 1: WorsttDQSCK

tDVAC(Clock) Reference: N/A

Test Summary: Pass Test Description: tDVAC(Clock)
Pass Limits:>= 35.0pstDVAC(Clock)490.7ps

Result Details:

Result Details
WorsttDVAC_Clock(See image)NotePlease refer to the JEDEC specification for actual limit.Min4.906973e-010sMax5.609934e-010sNumOfMeas4.828000e+003Differential Slew Rate6.156132e+000V/nsCH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseVIHdiff(AC)0.3VILdiff(AC)-0.3Sampling Points2000000

Trial 1

Trial 1: WorsttDVAC_Clock

tLZDQS Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: DQS low-impedance time from CK,/CK
Pass Limits:>= 2.2000nstLZDQS4.4609ns

Result Details:

Result Details
tLZDQS(See image)Number of burst(s) measured1.000000e+000NumOfMeas1.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UsetDQSCK Delay (cycle)3Sampling Points (Pts)2000000Min4.4609nsMax4.4609nsMean4.4609nsStdev0.0000000000000s

Trial 1

Trial 1: tLZDQS

tHZDQS Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: DQS high-impedance time from CK,/CK
Pass Limits:<= 5.4000nstHZDQS3.7919ns

Result Details:

Result Details
tHZDQS(See image)Number of burst(s) measured1CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UsetDQSCK Delay (cycle)3 Sampling Points (Pts)2000000Min3.792nsMax3.792nsMean3.792nsStdev0.000000000000s

Trial 1

Trial 1: tHZDQS

tQSH Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: FAIL Test Description: DQS output high time
Pass Limits:>= 450.0000000000mtCKtQSH336.9369000000mtCK

Result Details:

Result Details
Worst tQSH(See image)Number of burst(s) measured1.000000e+000NumOfMeas4.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min336.936900000mtCKMax404.061100000mtCKMean374.994200000mtCKStdev29.215310000mtCK

Trial 1

Trial 1: Worst tQSH

tQSL Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: DQS output low time
Pass Limits:>= 450.0000000000mtCKtQSL614.6386000000mtCK

Result Details:

Result Details
Worst tQSL(See image)Number of burst(s) measured1.000000e+000NumOfMeas3.000CH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseSampling Points (Pts)2000000Min614.638600000mtCKMax654.875000000mtCKMean634.497700000mtCKStdev20.123210000mtCK

Trial 1

Trial 1: Worst tQSL

tDVAC(Strobe) Reference: N/A

Test Summary: Pass Test Description: tDVAC(Strobe)
Pass Limits:>= 35.0pstDVAC(Strobe)343.8ps

Result Details:

Result Details
WorsttDVAC_DQS(See image)Number of burst(s) measured1NumOfMeas9.000NotePlease refer to the JEDEC specification for actual limit.Differential Slew Rate2.669037e+000V/nsCH1_PUTClockCH1_SrcCK_t,CK_cCH2_PUTStrobeCH2_SrcDQS0_t,DQS0_cCH3_PUTDataCH3_SrcDQ0,GndCH4_PUTPlease select a signalCH4_SrcNot In UseVIHdiff(AC)0.3VILdiff(AC)-0.3Sampling Points2000000Min344psMax568psMean458psStdev92ps

Trial 1

Trial 1: WorsttDVAC_DQS

tCK(abs) Rising Edge Measurements Reference:

Test Summary: FAIL Test Description: tCK(abs) Rising Edge Measurements
Pass Limits:>= 1.180nstCKabs Rising1.173ns

Result Details:

Result Details
Min1.173nsMax1.319nsAbs. Diff146.150psAverage1.255nsPeriods19.918000kMeasurements19.918000kWaveform SrcChannel 1tWorstCaseN/A

Next

tjit(CC) Rising Edge Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: tjit(CC) Rising Edge Measurements
Pass Limits:<= 140pstjitCC Rising77ps

Result Details:

Result Details
Min-88.917psMax77.308psAbs. Diff166.225psAverage2.119fsPeriods19.918000kMeasurements19.917000kWaveform SrcChannel 1tWorstCaseN/A

Next

tCK(avg) Rising Edge Measurements Reference: JEDEC Standard No. 79-3E, Table 64 (CL=10, CWL=7)

Test Summary: Pass Test Description: tCK(avg) Rising Edge Measurements
Pass Limits:[1.250ns to 100.000ns]tCKavg Rising1.254ns

Result Details:

Result Details
Min1.254nsMax1.256nsAbs. Diff1.341psAverage1.255nsPeriods19.918000kMeasurements19.719000kWaveform SrcChannel 1tWorstCaseN/A

Next

tjit(per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: FAIL Test Description: tjit(per) Rising Edge Measurements
Pass Limits:[-70ps to 70ps]tjitper Rising-83ps

Result Details:

Result Details
Min-82.600psMax64.473psAbs. Diff147.074psAverage0.000000000000sPeriods19.918000kMeasurements3.943800000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(2per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: FAIL Test Description: terr(2per) Rising Edge Measurements
Pass Limits:[-103ps to 103ps]terr2per Rising-126ps

Result Details:

Result Details
Min-125.834psMax91.088psAbs. Diff216.922psAverage0.0000000000000sPeriods19.918000kMeasurements3.924081000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(3per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: FAIL Test Description: terr(3per) Rising Edge Measurements
Pass Limits:[-122ps to 122ps]terr3per Rising-133ps

Result Details:

Result Details
Min-132.695psMax98.314psAbs. Diff231.009psAverage0.0000000000000sPeriods19.918000kMeasurements3.904362000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(4per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: terr(4per) Rising Edge Measurements
Pass Limits:[-136ps to 136ps]terr4per Rising-108ps

Result Details:

Result Details
Min-107.626psMax93.295psAbs. Diff200.921psAverage0.0000000000000sPeriods19.918000kMeasurements3.884643000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(5per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: terr(5per) Rising Edge Measurements
Pass Limits:[-147ps to 147ps]terr5per Rising125ps

Result Details:

Result Details
Min-97.611psMax125.212psAbs. Diff222.823psAverage0.0000000000000sPeriods19.918000kMeasurements3.864924000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(6per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: terr(6per) Rising Edge Measurements
Pass Limits:[-155ps to 155ps]terr6per Rising120ps

Result Details:

Result Details
Min-102.146psMax119.543psAbs. Diff221.689psAverage0.0000000000000sPeriods19.918000kMeasurements3.845205000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(7per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: terr(7per) Rising Edge Measurements
Pass Limits:[-163ps to 163ps]terr7per Rising111ps

Result Details:

Result Details
Min-66.708psMax111.226psAbs. Diff177.934psAverage0.0000000000000sPeriods19.918000kMeasurements3.825486000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(8per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: terr(8per) Rising Edge Measurements
Pass Limits:[-169ps to 169ps]terr8per Rising78ps

Result Details:

Result Details
Min-61.343psMax77.521psAbs. Diff138.864psAverage0.0000000000000sPeriods19.918000kMeasurements3.805767000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(9per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: terr(9per) Rising Edge Measurements
Pass Limits:[-175ps to 175ps]terr9per Rising78ps

Result Details:

Result Details
Min-66.037psMax78.166psAbs. Diff144.204psAverage0.0000000000000sPeriods19.918000kMeasurements3.786048000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(10per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: terr(10per) Rising Edge Measurements
Pass Limits:[-180ps to 180ps]terr10per Rising-88ps

Result Details:

Result Details
Min-87.549psMax81.346psAbs. Diff168.895psAverage0.0000000000000sPeriods19.918000kMeasurements3.766329000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(11per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: terr(11per) Rising Edge Measurements
Pass Limits:[-184ps to 184ps]terr11per Rising-125ps

Result Details:

Result Details
Min-125.016psMax92.194psAbs. Diff217.210psAverage0.0000000000000sPeriods19.918000kMeasurements3.746610000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(12per) Rising Edge Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: terr(12per) Rising Edge Measurements
Pass Limits:[-188ps to 188ps]terr12per Rising128ps

Result Details:

Result Details
Min-119.798psMax128.498psAbs. Diff248.297psAverage0.0000000000000sPeriods19.918000kMeasurements3.726891000MWaveform SrcChannel 1tWorstCaseN/A

Next

terr(nper) Rising Edge Measurements Reference: N/A

Test Summary: Pass Test Description: terr(nper) Rising Edge Measurements
Pass Limits:[-99.000000000000E36s to 99.000000000000E36s]terrnper Rising134ps

Result Details:

Result Details
Worst Subwindow size36.000Min-108.850psMax134.289psAbs. Diff243.138psAverage0.0000000000000sPeriods19.918000kMeasurements127.010079000MWaveform SrcChannel 1nper_min13nper_max50tWorstCaseN/A

Next

tCH Average High Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: tCH Average High Measurements
Pass Limits:[450.000000000mtCK(avg) to 550.000000000mtCK(avg)]tC High Pulse DC511.237865441mtCK(avg)

Result Details:

Result Details
Min508mtCK(avg)Max511mtCK(avg)Abs. Diff3mtCK(avg)Average510mtCK(avg)Periods19.919000kMeasurements19.719000ktWorstCaseN/AWaveform SrcChannel 1

Next

tCL Average Low Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: Pass Test Description: tCL Average LowMeasurements
Pass Limits:[450.000000000mtCK(avg) to 550.000000000mtCK(avg)]tC Low Pulse DC488.727837277mtCK(avg)

Result Details:

Result Details
Min489mtCK(avg)Max492mtCK(avg)Abs. Diff3mtCK(avg)Average490mtCK(avg)Periods19.919000kMeasurements19.719000ktWorstCaseN/AWaveform SrcChannel 1

Next

tjit(duty-high) Jitter Average High Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: FAIL Test Description: tjit(duty-high) Jitter Average High Measurements
Pass Limits:[-25ps to 25ps]tjit Duty High-43ps

Result Details:

Result Details
Min-43.191psMax36.237psAbs. Diff79.428psAverage-400E-27sPeriods19.919000kMeasurements3.944000000MWaveform SrcChannel 1tWorstCaseN/A

Next

tjit(duty-low) Jitter Average Low Measurements Reference: JEDEC Standard No. 79-3E, Table 68

Test Summary: FAIL Test Description: tjitduty-low Jitter Average LowMeasurements
Pass Limits:[-25ps to 25ps]tjit Duty Low49ps

Result Details:

Result Details
Min-44.331psMax49.038psAbs. Diff93.369psAverage60E-27sPeriods19.919000kMeasurements3.944000000MWaveform SrcChannel 1tWorstCaseN/A

Next

tCH(abs) Absolute clock HIGH pulse width Reference: JEDEC Standard No. 209-3, Table 64

Test Summary: Pass Test Description: tCH(abs) Absolute clock HIGH pulse width
Pass Limits:[430.000000000mtCK(avg) to 570.000000000mtCK(avg)]tCH(abs)475.264936017mtCK(avg)

Result Details:

Result Details
Min475.264936017mtCK(avg)Max538.149989642mtCK(avg)Abs. Diff62.885053624643mtCK(avg)Average509.498653408mtCK(avg)Pulses19.919000kMeasurements19.919000kWaveform SrcChannel 1

Next

tCL(abs) Absolute clock LOW pulse width Reference: JEDEC Standard No. 209-3, Table 64

Test Summary: Pass Test Description: tCL(abs) Absolute clock LOW pulse width
Pass Limits:[430.000000000mtCK(avg) to 570.000000000mtCK(avg)]tCL(abs)455.698713965mtCK(avg)

Result Details:

Result Details
Min455.698713965mtCK(avg)Max529.514270689mtCK(avg)Abs. Diff73.815556724196mtCK(avg)Average490.505330592mtCK(avg)Pulses19.919000kMeasurements19.919000kWaveform SrcChannel 1

Next

tCKE Reference: N/A

Test Summary: Pass Test Description: CKE Minimum Pulse Width
Pass Limits:>= 7.5000nstCKE2.9806830µs

Result Details:

Result Details
Worst tCKE(See image)NumOfMeas1.000CH1_PUTSupporting PinCH1_SrcCK_t,CK_cCH2_PUTPlease select a signalCH2_SrcNot In UseCH3_PUTPlease select a signalCH3_SrcNot In UseCH4_PUTPin Under TestCH4_SrcCKE,Gnd

Trial 1

Trial 1: Worst tCKE

tIPWCA Reference: JEDEC Standard No. 209-3, Table 118

Test Summary: Pass Test Description: tIPWCA
Pass Limits:>= 350.000000000mtCKtIPWCA16.064590000000tCK

Result Details:

Result Details
WorsttIPWCA(See image)Min2.008073e-008sMax1.850874e-007sNo Of Edge2.000000e+000CH1_PUTSupporting PinCH1_SrcCK_t,CK_cCH2_PUTPlease select a signalCH2_SrcNot In UseCH3_PUTPlease select a signalCH3_SrcNot In UseCH4_PUTPin Under TestCH4_SrcCA0,Gnd

Trial 1

Trial 1: WorsttIPWCA

Test Configuration Details
Device Description
LPDDR3	Yes
DDR3L	No
Comments	Channel 1, CK1, DQS1_1,DQ14_1,CA0_1
Test Mode	Compliance
Speed Grade	LPDDR3-1600
Test Session Details
Infiniium SW Version	04.60.0005
Infiniium Model Number	DSOX91604A
Infiniium Serial Number	MY51270009
Application SW Version	2.03
Debug Mode Used	No
Compliance Limits (official)	LPDDR3-1600 Test Limit
Probe (Channel 1)	Model: 1169A, Serial: US44002080, Head: N5381A, Atten: [Calibrated (27 NOV 2013 15:10:09), Using Cal Atten (3.1355E+000)], Skew: [Calibrated (27 NOV 2013 15:10:18), Using Cal Skew]
Probe (Channel 2)	Model: 1169A, Serial: US44005556, Head: N5381A, Atten: [Calibrated (27 NOV 2013 17:49:06), Using Cal Atten (3.1134E+000)], Skew: [Calibrated (27 NOV 2013 17:49:34), Using Cal Skew]
Probe (Channel 3)	Model: 1169A, Serial: US44005557, Head: N5381A, Atten: [Calibrated (27 NOV 2013 17:50:52), Using Cal Atten (3.1443E+000)], Skew: [Calibrated (27 NOV 2013 17:51:09), Using Cal Skew]
Probe (Channel 4)	Model: 1169A, Serial: US44005379, Head: N5425A, Atten: [Calibrated (27 NOV 2013 16:18:02), Using Cal Atten (3.0759E+000)], Skew: [Calibrated (27 NOV 2013 16:18:22), Using Cal Skew]
Last Test Date	2013-11-27 19:19:51 UTC -07:00

Test Statistics
Failed	19
Passed	75
Total	94

Margin Thresholds
Warning	< 2 %
Critical	< 0 %

Pass	# Failed	# Trials	Test Name	Actual Value	Margin	Pass Limits
	0	1	VIH.CA(AC)	1.219140000000V	62.6 %	VALUE >= VrefCA_Volt+AcLevels_CA_VoltV
	1	1	VIH.CA(DC)	1.245490000000V	-9.1 %	VrefCA_Volt+DcLevels_VoltV <= VALUE <= VDDCA_VoltV
	0	1	VIL.CA(AC)	-19.240000000mV	104.3 %	VALUE <= VrefCA_Volt-AcLevels_CA_VoltV
	1	1	VIL.CA(DC)	-19.240000000mV	-3.8 %	0.000000000000V <= VALUE <= VrefCA_Volt-DcLevels_VoltV
	0	1	VIH.DQ(AC)	967.608300000mV	29.0 %	VALUE >= VrefDQ_Volt+AcLevels_DQ_VoltV
	0	1	VIH.DQ(DC)	967.608300000mV	46.5 %	VrefDQ_Volt+DcLevels_VoltV <= VALUE <= VDDQ_VoltV
	0	1	VIL.DQ(AC)	428.115800000mV	4.9 %	VALUE <= VrefDQ_Volt-AcLevels_DQ_VoltV
	0	1	VIL.DQ(DC)	428.115800000mV	14.4 %	0.000000000000V <= VALUE <= VrefDQ_Volt-DcLevels_VoltV
	0	1	VSEH(Strobe)	845.571000000mV	3.1 %	VALUE >= VDDQ_Volt/2 + 0.220V
	0	1	VSEL(Strobe)	-1.224207000000V	422.2 %	VALUE <= VDDQ_Volt/2 - 0.220V
	0	1	VSEH(Clock)	1.056850000000V	28.9 %	VALUE >= VDDCA_Volt/2 + 0.220V
	0	1	VSEL(Clock)	-1.097450000000V	388.8 %	VALUE <= VDDCA_Volt/2 - 0.220V
	0	1	VOH(AC)	1.199150000000V	66.5 %	VALUE >= VrefDQ_Volt+0.12V
	0	1	VOH(DC)	1.199150000000V	11.0 %	VALUE >= 0.9*VDDQ_VoltV
	0	1	VOL(AC)	-40.670000000mV	108.5 %	VALUE <= VrefDQ_Volt-0.12V
	0	1	VOL(DC)	-40.670000000mV	133.9 %	VALUE <= 0.1*VDDQ_VoltV
	1	1	SRQseR	8.413856000000V/ns	-220.7 %	2.000000000000V/ns <= VALUE <= 4.000000000000V/ns
	1	1	SRQseF	914.063300000mV/ns	-54.3 %	2.000000000000V/ns <= VALUE <= 4.000000000000V/ns
	0	1	Overshoot amplitude (Address, Control, Clock, Chip Select, Clock Enable)	106.020000000mV	69.7 %	VALUE <= 350.000000000mV
	1	1	Overshoot area (Address, Control, Clock, Chip Select, Clock Enable)	5.327542000000V-ns	-523E+01 %	VALUE <= 100.000000000mV-ns
	0	1	Undershoot amplitude (Address, Control, Clock, Chip Select, Clock Enable)	151.420000000mV	56.7 %	VALUE <= 350.000000000mV
	0	1	Undershoot area (Address, Control, Clock, Chip Select, Clock Enable)	40.608730000mV-ns	59.4 %	VALUE <= 100.000000000mV-ns
	0	1	Overshoot amplitude (Data, Strobe, Mask)	111.160000000mV	68.2 %	VALUE <= 350.000000000mV
	0	1	Overshoot area (Data, Strobe, Mask)	38.385880000mV-ns	61.6 %	VALUE <= 100.000000000mV-ns
	0	1	Undershoot amplitude (Data, Strobe, Mask)	122.010000000mV	65.1 %	VALUE <= 350.000000000mV
	0	1	Undershoot area (Data, Strobe, Mask)	12.604710000mV-ns	87.4 %	VALUE <= 100.000000000mV-ns
	0	1	VIHdiff.CK(AC)	1.022890000000V	241.0 %	VALUE >= 2*(VIHAC_CA_Volt-VrefCA_Volt)V
	0	1	VIHdiff.CK(DC)	1.022890000000V	411.4 %	VALUE >= 2*(VIHDC_CA_Volt-VrefCA_Volt)V
	0	1	VILdiff.CK(AC)	-1.075080000000V	258.4 %	VALUE <= 2*(VILAC_CA_Volt-VrefCA_Volt)V
	0	1	VILdiff.CK(DC)	-1.075080000000V	437.5 %	VALUE <= 2*(VILDC_CA_Volt-VrefCA_Volt)V
	0	1	VIHdiff.DQS(AC)	681.500000000mV	127.2 %	VALUE >= 2*(VIHAC_DQ_Volt-VrefDQ_Volt)V
	0	1	VIHdiff.DQS(DC)	681.500000000mV	240.8 %	VALUE >= 2*(VIHDC_DQ_Volt-VrefDQ_Volt)V
	0	1	VILdiff.DQS(AC)	-1.073100000000V	257.7 %	VALUE <= 2*(VILAC_DQ_Volt-VrefDQ_Volt)V
	0	1	VILdiff.DQS(DC)	-1.073100000000V	436.6 %	VALUE <= 2*(VILDC_DQ_Volt-VrefDQ_Volt)V
	0	1	VOHdiff(AC)	711.800000000mV	196.6 %	VALUE >= 0.2*VDDQ_VoltV
	0	1	VOLdiff(AC)	-1.119400000000V	366.4 %	VALUE <= -0.2*VDDQ_VoltV
	1	1	SRQdiffR	2.122339000000V/ns	-46.9 %	4.000000000000V/ns <= VALUE <= 8.000000000000V/ns
	1	1	SRQdiffF	2.222282000000V/ns	-44.4 %	4.000000000000V/ns <= VALUE <= 8.000000000000V/ns
	0	1	tDS(base)	81ps	8.0 %	VALUE >= tDS_Limit_mins
	0	1	tDH(base)	239ps	139.0 %	VALUE >= tDH_Limit_mins
	0	1	tDS-Diff(derate)	81ps	17.4 %	VALUE >= tDSDiff_DeratedLimit_Mins
	0	1	tDH-Diff(derate)	239ps	168.5 %	VALUE >= tDHDiff_DeratedLimit_Mins
	0	1	tDIPW	1.217ns	177.9 %	VALUE >= 438ps
	0	1	tVAC(Data)	1.0647ns	294E+01 %	VALUE >= 35.0ps
	1	1	tWPRE	799.523500000mtCK	-0.1 %	VALUE >= 800.000000000mtCK
	0	1	tWPST	7.2000000000000E45tCK	180E+46 %	VALUE >= 400.0000000000mtCK
	0	1	tDQSS	1.090405000000tCK	31.9 %	750.000000000mtCK <= VALUE <= 1.250000000000tCK
	0	1	tDSS	536.118900000mtCK	168.1 %	VALUE >= 200.000000000mtCK
	0	1	tDSH	379.972700000mtCK	90.0 %	VALUE >= 200.000000000mtCK
	0	1	tDQSL	524.042900000mtCK	31.0 %	VALUE >= 400.000000000mtCK
	1	1	tDQSH	398.635500000mtCK	-0.3 %	VALUE >= 400.000000000mtCK
	0	1	tIS(base)	254.2ps	238.9 %	VALUE >= tIS_Limit_mins
	0	1	tIH(base)	330.9ps	230.9 %	VALUE >= tIH_Limit_mins
	0	1	tIS(derate)	254.2ps	142.8 %	VALUE >= tIS_DeratedLimit_Mins
	0	1	tIH(derate)	330.9ps	194.1 %	VALUE >= tIH_DeratedLimit_Mins
	0	1	tVAC(CS,CA)	19.9914ns	570E+02 %	VALUE >= 35.0ps
	0	1	tIPWCS	967.917100000mtCK	38.3 %	VALUE >= 700.000000000mtCK
	1	1	tDQSQ	211ps	-56.3 %	VALUE <= 135ps
	1	1	tQH	381.738100000mtCK	-15.2 %	VALUE >= 450.000000000mtCK
	0	1	tLZDQ	3.6663ns	66.7 %	VALUE >= 2.2000ns
	0	1	tHZDQ	4.4328ns	22.1 %	VALUE <= 5.6890ns
	0	1	tRPRE	1.338093000000tCK	48.7 %	VALUE >= 900.000000000mtCK
	1	1	tRPST	277.8743000000mtCK	-7.4 %	VALUE >= 300.0000000000mtCK
	0	1	tDQSCK	4.143ns	45.2 %	2.500ns <= VALUE <= 5.500ns
	0	1	tDVAC(Clock)	490.7ps	130E+01 %	VALUE >= 35.0ps
	0	1	tLZDQS	4.4609ns	102.8 %	VALUE >= 2.2000ns
	0	1	tHZDQS	3.7919ns	29.8 %	VALUE <= 5.4000ns
	1	1	tQSH	336.9369000000mtCK	-25.1 %	VALUE >= 450.0000000000mtCK
	0	1	tQSL	614.6386000000mtCK	36.6 %	VALUE >= 450.0000000000mtCK
	0	1	tDVAC(Strobe)	343.8ps	882.3 %	VALUE >= 35.0ps
	1	1	tCK(abs) Rising Edge Measurements	1.173ns	-0.6 %	VALUE >= 1.180ns
	0	1	tjit(CC) Rising Edge Measurements	77ps	45.0 %	VALUE <= 140ps
	0	1	tCK(avg) Rising Edge Measurements	1.254ns	0.0 %	1.250ns <= VALUE <= 100.000ns
	1	1	tjit(per) Rising Edge Measurements	-83ps	-9.3 %	-70ps <= VALUE <= 70ps
	1	1	terr(2per) Rising Edge Measurements	-126ps	-11.2 %	-103ps <= VALUE <= 103ps
	1	1	terr(3per) Rising Edge Measurements	-133ps	-4.5 %	-122ps <= VALUE <= 122ps
	0	1	terr(4per) Rising Edge Measurements	-108ps	10.3 %	-136ps <= VALUE <= 136ps
	0	1	terr(5per) Rising Edge Measurements	125ps	7.5 %	-147ps <= VALUE <= 147ps
	0	1	terr(6per) Rising Edge Measurements	120ps	11.3 %	-155ps <= VALUE <= 155ps
	0	1	terr(7per) Rising Edge Measurements	111ps	16.0 %	-163ps <= VALUE <= 163ps
	0	1	terr(8per) Rising Edge Measurements	78ps	26.9 %	-169ps <= VALUE <= 169ps
	0	1	terr(9per) Rising Edge Measurements	78ps	27.7 %	-175ps <= VALUE <= 175ps
	0	1	terr(10per) Rising Edge Measurements	-88ps	25.6 %	-180ps <= VALUE <= 180ps
	0	1	terr(11per) Rising Edge Measurements	-125ps	16.0 %	-184ps <= VALUE <= 184ps
	0	1	terr(12per) Rising Edge Measurements	128ps	16.0 %	-188ps <= VALUE <= 188ps
	0	1	terr(nper) Rising Edge Measurements	134ps	50.0 %	-99.000000000000E36s <= VALUE <= 99.000000000000E36s
	0	1	tCH Average High Measurements	511.237865441mtCK(avg)	38.8 %	450.000000000mtCK(avg) <= VALUE <= 550.000000000mtCK(avg)
	0	1	tCL Average Low Measurements	488.727837277mtCK(avg)	38.7 %	450.000000000mtCK(avg) <= VALUE <= 550.000000000mtCK(avg)
	1	1	tjit(duty-high) Jitter Average High Measurements	-43ps	-36.0 %	-25ps <= VALUE <= 25ps
	1	1	tjit(duty-low) Jitter Average Low Measurements	49ps	-48.0 %	-25ps <= VALUE <= 25ps
	0	1	tCH(abs) Absolute clock HIGH pulse width	475.264936017mtCK(avg)	32.3 %	430.000000000mtCK(avg) <= VALUE <= 570.000000000mtCK(avg)
	0	1	tCL(abs) Absolute clock LOW pulse width	455.698713965mtCK(avg)	18.4 %	430.000000000mtCK(avg) <= VALUE <= 570.000000000mtCK(avg)
	0	1	tCKE	2.9806830µs	396E+02 %	VALUE >= 7.5000ns
	0	1	tIPWCA	16.064590000000tCK	449E+01 %	VALUE >= 350.000000000mtCK

Summary of Results

Report Detail