HDMI Test Report

Overall Results:2 of 9 Tests Failed

Test Configuration Details
Device Description
HDMI Test TypeTMDS Physical Layer Tests
HDMI Specification2.0
Test Session Details
Infiniium SW Version04.50.0008
Infiniium Model NumberDSOX93204A
Infiniium Serial NumberMY53180105
Application SW Version1.99.9025
Debug Mode UsedYes
Probe (Channel 1)Model: 1169A Serial: US44002033 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.1036E+000) Skew: Not Calibrated, Using Default Skew
Probe (Channel 2)Model: 1169A Serial: US48470614 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.0989E+000) Skew: Not Calibrated, Using Default Skew
Probe (Channel 3)Model: 1169A Serial: US44000715 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.2949E+000) Skew: Not Calibrated, Using Default Skew
Probe (Channel 4)Model: 1169A Serial: US44000259 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.2029E+000) Skew: Not Calibrated, Using Default Skew
Last Test Date2013-09-09 09:28:23 UTC -07:00

Summary of Results

Margin Thresholds
Warning< 2 %
Critical< 0 %

Pass# Failed# TrialsTest NameActual ValueMarginSpec Range
017-9: Clock Jitter213 mTbit14.8 % VALUE <= 250 mTbit
017-4: Clock Rise Time91.393 ps21.9 % VALUE >= 75.000 ps
017-4: Clock Fall Time90.284 ps20.4 % VALUE >= 75.000 ps
017-8: Clock Duty Cycle(Minimum)49.29023.2 % >=40%
017-8: Clock Duty Cycle(Maximum)50.38016.0 % <=60%
017-10: D0 Mask Test0.00050.0 % No Mask Failures
017-10: D0 Data Jitter221 m26.3 % <=0.3Tbit
117-4: D0 Rise Time71.946 ps-4.1 % VALUE >= 75.000 ps
117-4: D0 Fall Time69.296 ps-7.6 % VALUE >= 75.000 ps


Report Detail


7-9: Clock Jitter Reference: Test ID 7-9
Test Summary: Pass Test Description: 2 Channels Connection Model: TMDS differential clock jitter must not exceed 0.25*Tbit, relative to the ideal Recovery Clock. For compliance, the DUT should output 27MHz(or 25MHz), 74.25MHz, 148.5MHz, and 222.75MHz for testing.
Test Limits:<= 250 mTbitClock Jitter213 mTbit
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Test Frequency(MHz)297.090# Edges16.000000000 MTbit(ps)336.598Clock Jitter(ps)71.780
Trial 1
Trial 1: Clock Jitter

7-4: Clock Rise Time Reference: Test ID 7-4
Test Summary: Pass Test Description: 2 Channels Connection Model: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psRaw Clock Transition Time91.393 ps
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Test Frequency(MHz)297.090Upper Threshold(%)80.000Lower Threshold(%)20.000# Edges10.997000 k
Trial 1
Trial 1: Raw Clock Transition Time

7-4: Clock Fall Time Reference: Test ID 7-4
Test Summary: Pass Test Description: 2 Channels Connection Model: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psRaw Clock Transition Time90.284 ps
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Test Frequency(MHz)297.090Upper Threshold(%)80.000Lower Threshold(%)20.000# Edges10.997000 k
Trial 1
Trial 1: Raw Clock Transition Time

7-8: Clock Duty Cycle(Minimum) Reference: Test ID 7-8
Test Summary: Pass Test Description: 2 Channels Connection Model: Clock duty cycle must be at least 40% and not more than 60%.The Source shall meet the AC specifications in Table 4-13 across all operating conditions specified in Table 4-11. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>=40%Clock Duty Cycle Minimum49.290
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Test Frequency(MHz)297.090# Edges10.000000 kTdutyMIN(ns)1.659
Trial 1
Trial 1: Clock Duty Cycle Minimum

7-8: Clock Duty Cycle(Maximum) Reference: Test ID 7-8
Test Summary: Pass Test Description: 2 Channels Connection Model: Clock duty cycle must be at least 40% and not more than 60%.The Source shall meet the AC specifications in Table 4-13 across all operating conditions specified in Table 4-11. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:<=60%Clock Duty Cycle Maximum50.380
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Test Frequency(MHz)297.090# Edges10.000000 kTdutyMAX(ns)1.696
Trial 1
Trial 1: Clock Duty Cycle Maximum

7-10: D0 Mask Test Reference: Test ID 7-10
Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:No Mask FailuresTotal # failures0.000
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Maximum Margin0.000000000000 sMaximum Margin (Vertical)0.000000000000 VEye Width(ps)262.790Eye Height(mV)667.740Data Lane AD0Test Frequency(MHz)297.090Mask Moved(ps)0.000# Acquisitions Point16.000000000 MTbit(ps)336.696RightJitterData(Tbit)221 mLeftJitterData(Tbit)219 mRightJitterData(ps)74.440LeftJitterData(ps)73.700Differential Swing Voltage(V)915 m
Trial 1
Trial 1: Total # failures

7-10: D0 Data Jitter Reference: Test ID 7-10
Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:<=0.3TbitTbitCheck221 m
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Data Lane AD0Test Frequency(MHz)297.090Mask Moved(ps)0.000# Acquisitions Point16.000000000 MTbit(ps)336.696RightJitterData(Tbit)221 mLeftJitterData(Tbit)219 mRightJitterData(ps)74.440LeftJitterData(ps)73.700Differential Swing Voltage(V)915 m
Trial 1
Trial 1: TbitCheck

7-4: D0 Rise Time Reference: Test ID 7-4
Test Summary: FAIL Test Description: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psTransition Time71.946 ps