6 true 2 0 Device Description HDMI Test Type TMDS Physical Layer Tests HDMI Specification 2.0 Test Session Details Infiniium SW Version 04.50.0008 Infiniium Model Number DSOX93204A Infiniium Serial Number MY53180105 Application SW Version 1.99.9025 Debug Mode Used Yes Probe (Channel 1) Model: 1169A Serial: US44002033 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.1036E+000) Skew: Not Calibrated, Using Default Skew Probe (Channel 2) Model: 1169A Serial: US48470614 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.0989E+000) Skew: Not Calibrated, Using Default Skew Probe (Channel 3) Model: 1169A Serial: US44000715 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.2949E+000) Skew: Not Calibrated, Using Default Skew Probe (Channel 4) Model: 1169A Serial: US44000259 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.2029E+000) Skew: Not Calibrated, Using Default Skew Last Test Date 2013-09-09 09:42:31 UTC -07:00 true Worst 12 12000 12001 1200000 200 201 20000 20100 2000000 2010000 400 401 501 502 50100 50200 5010000 5020000 2 3 9 22000 32000 32001 2200000 3200000 202 203 20200 20300 2020000 2030000 402 403 330 4 5 10 24000 34000 34001 2400000 3400000 204 205 20400 20500 2040000 2050000 404 405 331 6 7 90 26000 36000 36001 2600000 3600000 206 207 20600 20700 2060000 2070000 406 407 332 703 70300 7030000 704 70400 7040000 600 60000 6000000 705 70500 7050000 706 70600 7060000 601 60100 6010000 707 70700 7070000 708 70800 7080000 604 60400 6040000 709 70900 7090000 701 70100 7010000 605 60500 6050000 73 74 60 75 76 61 77 78 64 79 71 65 300 30000 301 30100 302 30200 82 81 80 85 84 83 1085 1084 1083 1184 1183 1284 1283 86 1086 1186 1286 87 1087 1187 1287 1900 2000 2001 2002 2010 2011 2020 2021 2022 2023 2030 2031 2950 3000 3001 3020 3030 3014 3015 3016 3017 3050 3950 4000 4014 4015 4020 4030 4050 HDMI HEAC true false 0001-01-01T00:00:00 Overall Summary + details of 1 worst trials

Trial Result Actual Value Margin HDMIAutomationConfig Test Frequency(MHz) # Edges Tbit(ps) Clock Jitter(ps)

Avg 229.4 mTbit 8.400 % StdDev NaN Tbit NaN % Range 0.000 Tbit 0.000 % Min 229.4 mTbit 8.400 % Max 229.4 mTbit 8.400 % Sum 229.4 mTbit 8.400 % Trial 1 (Worst) PASS 229 mTbit 8.4% Timing C 2 296.920 16.000000000 M 336.791 77.260 Trial 1

Trial 1

Trial 1: Clock Jitter report_files\12_1_1.png VALUE <= 250 mTbit 2 Channels Connection Model: TMDS differential clock jitter must not exceed 0.25*Tbit, relative to the ideal Recovery Clock. For compliance, the DUT should output 27MHz(or 25MHz), 74.25MHz, 148.5MHz, and 222.75MHz for testing. Test ID 7-9 <= 250 mTbit 7-9: Clock Jitter 12 false HDMIAutomationConfig Timing C 2 0 false true false 0 false HDMIAutomationConfig HDMIAutomationConfig false Test Frequency(MHz) 296.920 296.92019999999997 false true false 0 false Test Frequency(MHz) Test Frequency(MHz) false # Edges 16.000000000 M 16000000 false true false 0 false # Edges # Edges false Tbit(ps) 336.791 336.7908 false true false 0 false Tbit(ps) Tbit(ps) false Clock Jitter(ps) 77.260 77.26 false true false 0 false Clock Jitter(ps) Clock Jitter(ps) false Clock Jitter 229 mTbit Tbit 0.22940056557364394 false true false 0 report_files\12_1_1.png true Clock Jitter Clock Jitter false 8.3999999999999968 8.4 true 0

true 0.22940056557364394 0.052624619485507715 0.22940056557364394 0.22940056557364394 1 0 true Tbit 8.3999999999999968 70.559999999999945 8.3999999999999968 8.3999999999999968 1 0 true Margin Margin % 12 0 true 0 1 1 1 true Clock Jitter 8.4 229 mTbit 8.3999999999999968 1 2013-09-09T09:40:50.993164-07:00 false false 0001-01-01T00:00:00 Overall Summary + details of 1 worst trials

Trial Result Actual Value Margin HDMIAutomationConfig Test Frequency(MHz) Upper Threshold(%) Lower Threshold(%) # Edges

Avg 250.3 ps 233.7 % StdDev NaN ps NaN % Range 0.000 ps 0.000 % Min 250.3 ps 233.7 % Max 250.3 ps 233.7 % Sum 250.3 ps 233.7 % Trial 1 (Worst) PASS 250.278 ps 233.7% Timing C 2 296.920 80.000 20.000 11.003000 k Trial 1

Trial 1

Trial 1: Raw Clock Transition Time report_files\200_1_1.png VALUE >= 75.000 ps 2 Channels Connection Model: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test. Test ID 7-4 >= 75.000 ps 7-4: Clock Rise Time 200 false HDMIAutomationConfig Timing C 2 0 false true false 0 false HDMIAutomationConfig HDMIAutomationConfig false Test Frequency(MHz) 296.920 296.92019999999997 false true false 0 false Test Frequency(MHz) Test Frequency(MHz) false Upper Threshold(%) 80.000 80 false true false 0 false Upper Threshold(%) Upper Threshold(%) false Lower Threshold(%) 20.000 20 false true false 0 false Lower Threshold(%) Lower Threshold(%) false # Edges 11.003000 k 11003 false true false 0 false # Edges # Edges false Raw Clock Transition Time 250.278 ps ps 250.27800000000002 false true false 0 report_files\200_1_1.png true Raw Clock Transition Time Raw Clock Transition Time false 233.704 233.7 true 0

true 250.27800000000002 62639.077284000014 250.27800000000002 250.27800000000002 1 0 true ps 233.704 54617.559616000006 233.704 233.704 1 0 true Margin Margin % 200 0 true 0 1 1 1 true Raw Clock Transition Time 233.7 250.278 ps 233.704 1 2013-09-09T09:41:09.6484375-07:00 false false 0001-01-01T00:00:00 Overall Summary + details of 1 worst trials

Trial Result Actual Value Margin HDMIAutomationConfig Test Frequency(MHz) Upper Threshold(%) Lower Threshold(%) # Edges

Avg 261.9 ps 249.2 % StdDev NaN ps NaN % Range 0.000 ps 0.000 % Min 261.9 ps 249.2 % Max 261.9 ps 249.2 % Sum 261.9 ps 249.2 % Trial 1 (Worst) PASS 261.922 ps 249.2% Timing C 2 296.920 80.000 20.000 11.003000 k Trial 1

Trial 1

Trial 1: Raw Clock Transition Time report_files\201_1_1.png VALUE >= 75.000 ps 2 Channels Connection Model: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test. Test ID 7-4 >= 75.000 ps 7-4: Clock Fall Time 201 false HDMIAutomationConfig Timing C 2 0 false true false 0 false HDMIAutomationConfig HDMIAutomationConfig false Test Frequency(MHz) 296.920 296.92019999999997 false true false 0 false Test Frequency(MHz) Test Frequency(MHz) false Upper Threshold(%) 80.000 80 false true false 0 false Upper Threshold(%) Upper Threshold(%) false Lower Threshold(%) 20.000 20 false true false 0 false Lower Threshold(%) Lower Threshold(%) false # Edges 11.003000 k 11003 false true false 0 false # Edges # Edges false Raw Clock Transition Time 261.922 ps ps 261.92199999999997 false true false 0 report_files\201_1_1.png true Raw Clock Transition Time Raw Clock Transition Time false 249.22933333333336 249.2 true 0

true 261.92199999999997 68603.13408399999 261.92199999999997 261.92199999999997 1 0 true ps 249.22933333333336 62115.260593777792 249.22933333333336 249.22933333333336 1 0 true Margin Margin % 201 0 true 0 1 1 1 true Raw Clock Transition Time 249.2 261.922 ps 249.22933333333336 1 2013-09-09T09:41:16.3798828-07:00 false false 0001-01-01T00:00:00 Overall Summary + details of 1 worst trials

Trial Result Actual Value Margin HDMIAutomationConfig Test Frequency(MHz) # Edges TdutyMIN(ns)

Avg 49.81 24.53 % StdDev NaN NaN % Range 0.000 0.000 % Min 49.81 24.53 % Max 49.81 24.53 % Sum 49.81 24.53 % Trial 1 (Worst) PASS 49.810 24.5% Timing C 2 296.920 10.000000 k 1.678 Trial 1

Trial 1

Trial 1: Clock Duty Cycle Minimum report_files\501_1_1.png >=40% 2 Channels Connection Model: Clock duty cycle must be at least 40% and not more than 60%.The Source shall meet the AC specifications in Table 4-13 across all operating conditions specified in Table 4-11. For compliance, the DUT should output the highest supported pixel clock frequency during the test. Test ID 7-8 >=40% 7-8: Clock Duty Cycle(Minimum) 501 false HDMIAutomationConfig Timing C 2 0 false true false 0 false HDMIAutomationConfig HDMIAutomationConfig false Test Frequency(MHz) 296.920 296.92019999999997 false true false 0 false Test Frequency(MHz) Test Frequency(MHz) false # Edges 10.000000 k 10000 false true false 0 false # Edges # Edges false TdutyMIN(ns) 1.678 1.67772 false true false 0 false TdutyMIN(ns) TdutyMIN(ns) false Clock Duty Cycle Minimum 49.810 49.81 false true false 0 report_files\501_1_1.png true Clock Duty Cycle Minimum Clock Duty Cycle Minimum false 24.525000000000006 24.5 true 0

true 49.81 2481.0361000000003 49.81 49.81 1 0 true 24.525000000000006 601.47562500000026 24.525000000000006 24.525000000000006 1 0 true Margin Margin % 501 0 true 0 1 1 1 true Clock Duty Cycle Minimum 24.5 49.810 24.525000000000006 1 2013-09-09T09:41:23.8496093-07:00 false false 0001-01-01T00:00:00 Overall Summary + details of 1 worst trials

Trial Result Actual Value Margin HDMIAutomationConfig Test Frequency(MHz) # Edges TdutyMAX(ns)

Avg 50.90 15.17 % StdDev NaN NaN % Range 0.000 0.000 % Min 50.90 15.17 % Max 50.90 15.17 % Sum 50.90 15.17 % Trial 1 (Worst) PASS 50.900 15.2% Timing C 2 296.920 10.000000 k 1.714 Trial 1

Trial 1

Trial 1: Clock Duty Cycle Maximum report_files\502_1_1.png <=60% 2 Channels Connection Model: Clock duty cycle must be at least 40% and not more than 60%.The Source shall meet the AC specifications in Table 4-13 across all operating conditions specified in Table 4-11. For compliance, the DUT should output the highest supported pixel clock frequency during the test. Test ID 7-8 <=60% 7-8: Clock Duty Cycle(Maximum) 502 false HDMIAutomationConfig Timing C 2 0 false true false 0 false HDMIAutomationConfig HDMIAutomationConfig false Test Frequency(MHz) 296.920 296.92019999999997 false true false 0 false Test Frequency(MHz) Test Frequency(MHz) false # Edges 10.000000 k 10000 false true false 0 false # Edges # Edges false TdutyMAX(ns) 1.714 1.7144300000000001 false true false 0 false TdutyMAX(ns) TdutyMAX(ns) false Clock Duty Cycle Maximum 50.900 50.9 false true false 0 report_files\502_1_1.png true Clock Duty Cycle Maximum Clock Duty Cycle Maximum false 15.16666666666667 15.2 true 0

true 50.9 2590.81 50.9 50.9 1 0 true 15.16666666666667 230.02777777777786 15.16666666666667 15.16666666666667 1 0 true Margin Margin % 502 0 true 0 1 1 1 true Clock Duty Cycle Maximum 15.2 50.900 15.16666666666667 1 2013-09-09T09:41:46.765625-07:00 false false 0001-01-01T00:00:00 Overall Summary + details of 1 worst trials

Trial Result Actual Value Margin Maximum Margin (s) Maximum Margin (Vertical) (V) HDMIAutomationConfig Eye Width(ps) Eye Height(mV) Data Lane A Test Frequency(MHz) Mask Moved(ps) # Acquisitions Point Tbit(ps) RightJitterData(Tbit) LeftJitterData(Tbit) RightJitterData(ps) LeftJitterData(ps) Differential Swing Voltage(V)

Avg 0.000 50.00 % -1.218 ps 0.000 V StdDev NaN NaN % NaN s NaN V Range 0.000 0.000 % 0.000 s 0.000 V Min 0.000 50.00 % -1.218 ps 0.000 V Max 0.000 50.00 % -1.218 ps 0.000 V Sum 0.000 50.00 % -1.218 ps 0.000 V Trial 1 (Worst) PASS 0.000 50.0% -1 ps 0.000000000000 V Timing C 2 247.160 490.320 D0 296.920 1.200 16.000000000 M 336.695 268 m 265 m 90.080 89.330 887 m Trial 1

Trial 1

Trial 1: Total # failures report_files\2_1_1.png No Mask Failures For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements. Test ID 7-10 No Mask Failures 7-10: D0 Mask Test 2 false HDMIAutomationConfig Timing C 2 0 false true false 0 false HDMIAutomationConfig HDMIAutomationConfig false Maximum Margin -1 ps s -1.218182E-12 false true false 0 true Maximum Margin Maximum Margin false Maximum Margin (Vertical) 0.000000000000 V V 0 false true false 0 true Maximum Margin (Vertical) Maximum Margin (Vertical) false Eye Width(ps) 247.160 247.16 false true false 0 false Eye Width(ps) Eye Width(ps) false Eye Height(mV) 490.320 490.32 false true false 0 false Eye Height(mV) Eye Height(mV) false Data Lane A D0 0 false true false 0 false Data Lane A Data Lane A false Test Frequency(MHz) 296.920 296.92019999999997 false true false 0 false Test Frequency(MHz) Test Frequency(MHz) false Mask Moved(ps) 1.200 1.2 false true false 0 false Mask Moved(ps) Mask Moved(ps) false # Acquisitions Point 16.000000000 M 16000000 false true false 0 false # Acquisitions Point # Acquisitions Point false Tbit(ps) 336.695 336.6952 false true false 0 false Tbit(ps) Tbit(ps) false RightJitterData(Tbit) 268 m 0.26754168161589476 false true false 0 false RightJitterData(Tbit) RightJitterData(Tbit) false LeftJitterData(Tbit) 265 m 0.26531414763263628 false true false 0 false LeftJitterData(Tbit) LeftJitterData(Tbit) false RightJitterData(ps) 90.080 90.08 false true false 0 false RightJitterData(ps) RightJitterData(ps) false LeftJitterData(ps) 89.330 89.33 false true false 0 false LeftJitterData(ps) LeftJitterData(ps) false Differential Swing Voltage(V) 887 m 0.88742 false true false 0 false Differential Swing Voltage(V) Differential Swing Voltage(V) false Total # failures 0.000 0 false true false 0 report_files\2_1_1.png true Total # failures Total # failures false 50 50.0 true 0

true 0 0 0 0 1 0 true 50 2500 50 50 1 0 true Margin Margin % -1.218182E-12 1.4839673851239998E-24 -1.218182E-12 -1.218182E-12 1 0 true Maximum Margin Maximum Margin s 0 0 0 0 1 1 true Maximum Margin (Vertical) Maximum Margin (Vertical) V 2 0 -1.218182E-12 1.4839673851239998E-24 -1.218182E-12 -1.218182E-12 1 0 true Maximum Margin Maximum Margin s 0 0 0 0 1 1 true Maximum Margin (Vertical) Maximum Margin (Vertical) V true 0 1 1 1 true Total # failures 50.0 0.000 50 1 2013-09-09T09:41:50.3017578-07:00 false false 0001-01-01T00:00:00 Overall Summary + details of 1 worst trials

Trial Result Actual Value Margin HDMIAutomationConfig Data Lane A Test Frequency(MHz) Mask Moved(ps) # Acquisitions Point Tbit(ps) RightJitterData(Tbit) LeftJitterData(Tbit) RightJitterData(ps) LeftJitterData(ps) Differential Swing Voltage(V)

Avg 267.5 m 10.67 % StdDev NaN NaN % Range 0.000 0.000 % Min 267.5 m 10.67 % Max 267.5 m 10.67 % Sum 267.5 m 10.67 % Trial 1 (Worst) PASS 268 m 10.7% Timing C 2 D0 296.920 1.200 16.000000000 M 336.695 268 m 265 m 90.080 89.330 887 m Trial 1

Trial 1

Trial 1: TbitCheck report_files\3_1_1.png <=0.3Tbit For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements. Test ID 7-10 <=0.3Tbit 7-10: D0 Data Jitter 3 false HDMIAutomationConfig Timing C 2 0 false true false 0 false HDMIAutomationConfig HDMIAutomationConfig false Data Lane A D0 0 false true false 0 false Data Lane A Data Lane A false Test Frequency(MHz) 296.920 296.92019999999997 false true false 0 false Test Frequency(MHz) Test Frequency(MHz) false Mask Moved(ps) 1.200 1.2 false true false 0 false Mask Moved(ps) Mask Moved(ps) false # Acquisitions Point 16.000000000 M 16000000 false true false 0 false # Acquisitions Point # Acquisitions Point false Tbit(ps) 336.695 336.6952 false true false 0 false Tbit(ps) Tbit(ps) false RightJitterData(Tbit) 268 m 0.26754168161589476 false true false 0 false RightJitterData(Tbit) RightJitterData(Tbit) false LeftJitterData(Tbit) 265 m 0.26531414763263628 false true false 0 false LeftJitterData(Tbit) LeftJitterData(Tbit) false RightJitterData(ps) 90.080 90.08 false true false 0 false RightJitterData(ps) RightJitterData(ps) false LeftJitterData(ps) 89.330 89.33 false true false 0 false LeftJitterData(ps) LeftJitterData(ps) false Differential Swing Voltage(V) 887 m 0.88742 false true false 0 false Differential Swing Voltage(V) Differential Swing Voltage(V) false TbitCheck 268 m 0.2675417 false true false 0 report_files\3_1_1.png true TbitCheck TbitCheck false 10.666666666666657 10.7 true 0

true 0.2675417 0.07157856123888999 0.2675417 0.2675417 1 0 true 10.666666666666657 113.77777777777757 10.666666666666657 10.666666666666657 1 0 true Margin Margin % 3 0 true 0 1 1 1 true TbitCheck 10.7 268 m 10.666666666666657 1 2013-09-09T09:42:14.9238281-07:00 false false 0001-01-01T00:00:00 Overall Summary + details of 1 worst trials

Trial Result Actual Value Margin HDMIAutomationConfig Test Frequency(MHz) Data Lane A Upper Threshold(%) Lower Threshold(%) #Edge

Avg 79.40 ps 5.861 % StdDev NaN ps NaN % Range 0.000 ps 0.000 % Min 79.40 ps 5.861 % Max 79.40 ps 5.861 % Sum 79.40 ps 5.861 % Trial 1 (Worst) PASS 79.396 ps 5.9% Timing C 2 296.920 D0 80.000 20.000 29.225000 k Trial 1

Trial 1

Trial 1: Transition Time report_files\202_1_1.png VALUE >= 75.000 ps The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test. Test ID 7-4 >= 75.000 ps 7-4: D0 Rise Time 202 false HDMIAutomationConfig Timing C 2 0 false true false 0 false HDMIAutomationConfig HDMIAutomationConfig false Test Frequency(MHz) 296.920 296.92019999999997 false true false 0 false Test Frequency(MHz) Test Frequency(MHz) false Data Lane A D0 0 false true false 0 false Data Lane A Data Lane A false Upper Threshold(%) 80.000 80 false true false 0 false Upper Threshold(%) Upper Threshold(%) false Lower Threshold(%) 20.000 20 false true false 0 false Lower Threshold(%) Lower Threshold(%) false #Edge 29.225000 k 29225 false true false 0 false #Edge #Edge false Transition Time 79.396 ps ps 79.3962 false true false 0 report_files\202_1_1.png true Transition Time Transition Time false 5.8613333333333344 5.9 true 0

true 79.3962 6303.756574439999 79.3962 79.3962 1 0 true ps 5.8613333333333344 34.355228444444457 5.8613333333333344 5.8613333333333344 1 0 true Margin Margin % 202 0 true 0 1 1 1 true Transition Time 5.9 79.396 ps 5.8613333333333344 1 2013-09-09T09:42:18.9697265-07:00 false false 0001-01-01T00:00:00 Overall Summary + details of 1 worst trials

Trial Result Actual Value Margin HDMIAutomationConfig Test Frequency(MHz) Data Lane A Upper Threshold(%) Lower Threshold(%) #Edge

Avg 75.74 ps 985.3 m% StdDev NaN ps NaN % Range 0.000 ps 0.000 % Min 75.74 ps 985.3 m% Max 75.74 ps 985.3 m% Sum 75.74 ps 985.3 m% Trial 1 (Worst) PASS 75.740 ps 1.0% Timing C 2 296.920 D0 80.000 20.000 28.586000 k Trial 1

Trial 1

Trial 1: Transition Time report_files\203_1_1.png VALUE >= 75.000 ps The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test. Test ID 7-4 >= 75.000 ps 7-4: D0 Fall Time 203 false HDMIAutomationConfig Timing C 2 0 false true false 0 false HDMIAutomationConfig HDMIAutomationConfig false Test Frequency(MHz) 296.920 296.92019999999997 false true false 0 false Test Frequency(MHz) Test Frequency(MHz) false Data Lane A D0 0 false true false 0 false Data Lane A Data Lane A false Upper Threshold(%) 80.000 80 false true false 0 false Upper Threshold(%) Upper Threshold(%) false Lower Threshold(%) 20.000 20 false true false 0 false Lower Threshold(%) Lower Threshold(%) false #Edge 28.586000 k 28586 false true false 0 false #Edge #Edge false Transition Time 75.740 ps ps 75.739499999999992 false true false 0 report_files\203_1_1.png true Transition Time Transition Time false 0.98533333333333906 1.0 true 0

true 75.739499999999992 5736.4718602499988 75.739499999999992 75.739499999999992 1 0 true ps 0.98533333333333906 0.97088177777778906 0.98533333333333906 0.98533333333333906 1 0 true Margin Margin % 203 0 true 0 1 1 1 true Transition Time 1.0 75.740 ps 0.98533333333333906 1 2013-09-09T09:42:24.9208984-07:00 false false