HDMI
Test Report

Overall Results:0 of 9 Tests Failed

Test Configuration Details

Device Description

HDMI Test
Type

TMDS Physical Layer Tests

HDMI
Specification

2.0

Test Session Details

Infiniium SW
Version

04.50.0008

Infiniium Model
Number

DSOX93204A

Infiniium Serial
Number

MY53180105

Application SW
Version

1.99.9025

Debug Mode
Used

Yes

Probe (Channel
1)

Model: 1169A Serial: US44002033 Head: N5380A/B Atten: Not Calibrated,
Using Default Atten (2.1036E+000) Skew: Not Calibrated, Using Default
Skew

Probe (Channel
2)

Model: 1169A Serial: US48470614 Head: N5380A/B Atten: Not Calibrated,
Using Default Atten (2.0989E+000) Skew: Not Calibrated, Using Default
Skew

Probe (Channel
3)

Model: 1169A Serial: US44000715 Head: N5380A/B Atten: Not Calibrated,
Using Default Atten (2.2949E+000) Skew: Not Calibrated, Using Default
Skew

Probe (Channel
4)

Model: 1169A Serial: US44000259 Head: N5380A/B Atten: Not Calibrated,
Using Default Atten (2.2029E+000) Skew: Not Calibrated, Using Default
Skew

Last Test
Date

2013-09-09 09:42:31 UTC -07:00

Summary of Results

Margin Thresholds

Warning

< 2 %

Critical

< 0 %

Pass

# Failed

# Trials

Test Name

Actual Value

Margin

Spec Range

0

1

7-9:
Clock Jitter

229 mTbit

8.4 %

VALUE <= 250 mTbit

0

1

7-4:
Clock Rise Time

250.278 ps

233.7 %

VALUE >= 75.000 ps

0

1

7-4:
Clock Fall Time

261.922 ps

249.2 %

VALUE >= 75.000 ps

0

1

7-8:
Clock Duty Cycle(Minimum)

49.810

24.5 %

>=40%

0

1

7-8:
Clock Duty Cycle(Maximum)

50.900

15.2 %

<=60%

0

1

7-10:
D0 Mask Test

0.000

50.0 %

No Mask Failures

0

1

7-10:
D0 Data Jitter

268 m

10.7 %

<=0.3Tbit

0

1

7-4:
D0 Rise Time

79.396 ps

5.9 %

VALUE >= 75.000 ps

0

1

7-4:
D0 Fall Time

75.740 ps

1.0 %

VALUE >= 75.000 ps

Report Detail

7-9: Clock Jitter Reference:
Test ID 7-9
Test
Summary: Pass
Test Description: 2 Channels
Connection Model: TMDS differential clock jitter must not exceed 0.25*Tbit,
relative to the ideal Recovery Clock. For compliance, the DUT should output
27MHz(or 25MHz), 74.25MHz, 148.5MHz, and 222.75MHz for testing.
Test
Limits:<= 250 mTbitClock Jitter229
mTbit

Result
Details:
Result
Details
HDMIAutomationConfigTiming C
2Test
Frequency(MHz)296.920# Edges16.000000000 MTbit(ps)336.791Clock Jitter(ps)77.260

Trial
1

Trial 1: Clock Jitter

7-4: Clock Rise Time Reference:
Test ID 7-4
Test
Summary: Pass
Test Description: 2 Channels
Connection Model: The transition time is defined as the time interval between
the normalized 20% and 80% amplitude levels. For compliance, the DUT should
output the highest supported pixel clock frequency during the
test.
Test Limits:>= 75.000
psRaw Clock
Transition Time250.278 ps

Result
Details:
Result
Details
HDMIAutomationConfigTiming C
2Test
Frequency(MHz)296.920Upper Threshold(%)80.000Lower Threshold(%)20.000# Edges11.003000 k

Trial
1

Trial 1: Raw Clock Transition Time

7-4: Clock Fall Time Reference:
Test ID 7-4
Test
Summary: Pass
Test Description: 2 Channels
Connection Model: The transition time is defined as the time interval between
the normalized 20% and 80% amplitude levels. For compliance, the DUT should
output the highest supported pixel clock frequency during the
test.
Test Limits:>= 75.000
psRaw Clock
Transition Time261.922 ps

Result
Details:
Result
Details
HDMIAutomationConfigTiming C
2Test
Frequency(MHz)296.920Upper Threshold(%)80.000Lower Threshold(%)20.000# Edges11.003000 k

Trial
1

Trial 1: Raw Clock Transition Time

7-8: Clock Duty Cycle(Minimum)
Reference: Test ID 7-8
Test
Summary: Pass
Test Description: 2 Channels
Connection Model: Clock duty cycle must be at least 40% and not more than
60%.The Source shall meet the AC specifications in Table 4-13 across all
operating conditions specified in Table 4-11. For compliance, the DUT should
output the highest supported pixel clock frequency during the
test.
Test Limits:>=40%Clock Duty Cycle Minimum49.810

Result
Details:
Result
Details
HDMIAutomationConfigTiming C
2Test
Frequency(MHz)296.920# Edges10.000000 kTdutyMIN(ns)1.678

Trial
1

Trial 1: Clock Duty Cycle Minimum

7-8: Clock Duty Cycle(Maximum)
Reference: Test ID 7-8
Test
Summary: Pass
Test Description: 2 Channels
Connection Model: Clock duty cycle must be at least 40% and not more than
60%.The Source shall meet the AC specifications in Table 4-13 across all
operating conditions specified in Table 4-11. For compliance, the DUT should
output the highest supported pixel clock frequency during the
test.
Test Limits:<=60%Clock Duty Cycle Maximum50.900

Result
Details:
Result
Details
HDMIAutomationConfigTiming C
2Test
Frequency(MHz)296.920# Edges10.000000 kTdutyMAX(ns)1.714

Trial
1

Trial 1: Clock Duty Cycle Maximum

7-10: D0 Mask Test Reference:
Test ID 7-10
Test
Summary: Pass
Test Description: For all
channels under all operating conditions specified in Table 4-11 . The Source
shall have output levels at TP1, which meet the normalized eye diagram
requirements.
Test Limits:No
Mask FailuresTotal #
failures0.000

Result
Details:
Result
Details
HDMIAutomationConfigTiming C
2Maximum
Margin-1 psMaximum Margin
(Vertical)0.000000000000 VEye Width(ps)247.160Eye Height(mV)490.320Data Lane AD0Test Frequency(MHz)296.920Mask Moved(ps)1.200# Acquisitions Point16.000000000
MTbit(ps)336.695RightJitterData(Tbit)268 mLeftJitterData(Tbit)265
mRightJitterData(ps)90.080LeftJitterData(ps)89.330Differential Swing Voltage(V)887
m

Trial
1

Trial 1: Total # failures

7-10: D0 Data Jitter Reference:
Test ID 7-10
Test
Summary: Pass
Test Description: For all
channels under all operating conditions specified in Table 4-11 . The Source
shall have output levels at TP1, which meet the normalized eye diagram
requirements.
Test Limits:<=0.3TbitTbitCheck268 m

Result
Details:
Result
Details
HDMIAutomationConfigTiming C
2Data Lane
AD0Test Frequency(MHz)296.920Mask Moved(ps)1.200# Acquisitions Point16.000000000
MTbit(ps)336.695RightJitterData(Tbit)268 mLeftJitterData(Tbit)265
mRightJitterData(ps)90.080LeftJitterData(ps)89.330Differential Swing Voltage(V)887
m

Trial
1

Trial 1: TbitCheck

7-4: D0 Rise Time Reference:
Test ID 7-4
Test
Summary: Pass
Test Description: The
transition time is defined as the time interval between the normalized 20% and
80% amplitude levels. For compliance, the DUT should output the highest
supported pixel clock frequency during the test.
Test
Limits:>= 75.000 psTransition Time79.396 ps

Result
Details:
Result
Details
HDMIAutomationConfigTiming C
2Test
Frequency(MHz)296.920Data Lane AD0Upper Threshold(%)80.000Lower Threshold(%)20.000#Edge29.225000 k

Trial
1

Trial 1: Transition Time

7-4: D0 Fall Time Reference:
Test ID 7-4
Test
Summary: Pass
Test Description: The
transition time is defined as the time interval between the normalized 20% and
80% amplitude levels. For compliance, the DUT should output the highest
supported pixel clock frequency during the test.
Test
Limits:>= 75.000 psTransition Time75.740 ps

Result
Details:
Result
Details
HDMIAutomationConfigTiming C
2Test
Frequency(MHz)296.920Data Lane AD0Upper Threshold(%)80.000Lower Threshold(%)20.000#Edge28.586000 k

Trial
1

Trial 1: Transition Time