HDMI Test Report

Overall Results:0 of 17 Tests Failed

Test Configuration Details
Device Description
HDMI Specification2.0
HDMI Test TypeTMDS Physical Layer Tests
Test ModeCompliance Mode
Test Session Details
Infiniium SW Version04.50.0008
Infiniium Model NumberDSOX93204A
Infiniium Serial NumberMY53180105
Application SW Version1.99.9027
Debug Mode UsedNo
Probe (Channel 1)Model: 1169A Serial: US44000259 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.2029E+000) Skew: Not Calibrated, Using Default Skew
Probe (Channel 2)Model: 1169A Serial: US49413460 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.0148E+000) Skew: Not Calibrated, Using Default Skew
Probe (Channel 3)Model: 1169A Serial: US49412951 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.2029E+000) Skew: Not Calibrated, Using Default Skew
Probe (Channel 4)Model: 1169A Serial: US49412941 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.1765E+000) Skew: Not Calibrated, Using Default Skew
Last Test Date2013-09-12 14:39:02 UTC -07:00

Summary of Results

Margin Thresholds
Warning< 2 %
Critical< 0 %

Pass# Failed# TrialsTest NameWorst ActualWorst MarginSpec Range
017-9: Clock Jitter180 mTbit28.0 % VALUE <= 250 mTbit
017-4: Clock Rise Time236.575 ps215.4 % VALUE >= 75.000 ps
017-4: Clock Fall Time239.451 ps219.3 % VALUE >= 75.000 ps
017-8: Clock Duty Cycle(Minimum)49.48023.7 % >=40%
017-8: Clock Duty Cycle(Maximum)50.10016.5 % <=60%
017-10: D0 Mask Test0.00050.0 % No Mask Failures
017-10: D0 Data Jitter172 m42.7 % <=0.3Tbit
017-4: D0 Rise Time144.511 ps92.7 % VALUE >= 75.000 ps
017-4: D0 Fall Time150.023 ps100.0 % VALUE >= 75.000 ps
017-10: D1 Mask Test0.00050.0 % No Mask Failures
037-10: D1 Data Jitter172 m42.7 % <=0.3Tbit
037-4: D1 Rise Time146.070 ps94.8 % VALUE >= 75.000 ps
037-4: D1 Fall Time147.491 ps96.7 % VALUE >= 75.000 ps
027-10: D2 Mask Test0.00050.0 % No Mask Failures
037-10: D2 Data Jitter179 m40.3 % <=0.3Tbit
037-4: D2 Rise Time146.844 ps95.8 % VALUE >= 75.000 ps
037-4: D2 Fall Time147.883 ps97.2 % VALUE >= 75.000 ps


Report Detail


7-9: Clock Jitter Reference: Test ID 7-9
Test Summary: Pass Test Description: 2 Channels Connection Model: TMDS differential clock jitter must not exceed 0.25*Tbit, relative to the ideal Recovery Clock. For compliance, the DUT should output 27MHz(or 25MHz), 74.25MHz, 148.5MHz, and 222.75MHz for testing.
Test Limits:<= 250 mTbitClock Jitter180 mTbit
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Test Frequency(MHz)296.726# Edges16.000000000 MTbit(ps)337.012Clock Jitter(ps)60.630
Trial 1
Trial 1: Clock Jitter

7-4: Clock Rise Time Reference: Test ID 7-4
Test Summary: Pass Test Description: 2 Channels Connection Model: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psRaw Clock Transition Time236.575 ps
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Test Frequency(MHz)296.726Upper Threshold(%)80.000Lower Threshold(%)20.000# Edges10.999000 k
Trial 1
Trial 1: Raw Clock Transition Time

7-4: Clock Fall Time Reference: Test ID 7-4
Test Summary: Pass Test Description: 2 Channels Connection Model: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psRaw Clock Transition Time239.451 ps
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Test Frequency(MHz)296.726Upper Threshold(%)80.000Lower Threshold(%)20.000# Edges10.999000 k
Trial 1
Trial 1: Raw Clock Transition Time

7-8: Clock Duty Cycle(Minimum) Reference: Test ID 7-8
Test Summary: Pass Test Description: 2 Channels Connection Model: Clock duty cycle must be at least 40% and not more than 60%.The Source shall meet the AC specifications in Table 4-13 across all operating conditions specified in Table 4-11. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>=40%Clock Duty Cycle Minimum49.480
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Test Frequency(MHz)296.726# Edges10.000000 kTdutyMIN(ns)1.668
Trial 1
Trial 1: Clock Duty Cycle Minimum

7-8: Clock Duty Cycle(Maximum) Reference: Test ID 7-8
Test Summary: Pass Test Description: 2 Channels Connection Model: Clock duty cycle must be at least 40% and not more than 60%.The Source shall meet the AC specifications in Table 4-13 across all operating conditions specified in Table 4-11. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:<=60%Clock Duty Cycle Maximum50.100
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Test Frequency(MHz)296.726# Edges10.000000 kTdutyMAX(ns)1.689
Trial 1
Trial 1: Clock Duty Cycle Maximum

7-10: D0 Mask Test Reference: Test ID 7-10
Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:No Mask FailuresTotal # failures0.000
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Maximum Margin0.000000000000 sMaximum Margin (Vertical)0.000000000000 VEye Width(ps)279.170Eye Height(mV)467.740Data Lane AD0Test Frequency(MHz)296.726Mask Moved(ps)0.000# Acquisitions Point16.000000000 MTbit(ps)337.031RightJitterData(Tbit)172 mLeftJitterData(Tbit)172 mRightJitterData(ps)58.070LeftJitterData(ps)58.070Differential Swing Voltage(V)1.064
Trial 1
Trial 1: Total # failures

7-10: D0 Data Jitter Reference: Test ID 7-10
Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:<=0.3TbitTbitCheck172 m
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Data Lane AD0Test Frequency(MHz)296.726Mask Moved(ps)0.000# Acquisitions Point16.000000000 MTbit(ps)337.031RightJitterData(Tbit)172 mLeftJitterData(Tbit)172 mRightJitterData(ps)58.070LeftJitterData(ps)58.070Differential Swing Voltage(V)1.064
Trial 1
Trial 1: TbitCheck

7-4: D0 Rise Time Reference: Test ID 7-4
Test Summary: Pass Test Description: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psTransition Time144.511 ps
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Test Frequency(MHz)296.726Data Lane AD0Upper Threshold(%)80.000Lower Threshold(%)20.000#Edge16.356000 k
Trial 1
Trial 1: Transition Time

7-4: D0 Fall Time Reference: Test ID 7-4
Test Summary: Pass Test Description: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psTransition Time150.023 ps
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Test Frequency(MHz)296.726Data Lane AD0Upper Threshold(%)80.000Lower Threshold(%)20.000#Edge17.779000 k
Trial 1
Trial 1: Transition Time

7-10: D1 Mask Test Reference: Test ID 7-10
Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:No Mask FailuresTotal # failures0.000
Result Details:
Result Details
HDMIAutomationConfigTiming C 2Data Lane AD1Test Frequency(MHz)296.726Mask Moved(ps)0.000# Acquisitions Point16.000000000 MTbit(ps)337.031RightJitterData(Tbit)172 mLeftJitterData(Tbit)172 mRightJitterData(ps)58.070LeftJitterData(ps)58.070Differential Swing Voltage(V)1.064
Trial 1
Trial 1: Total # failures

7-10: D1 Data Jitter Reference: Test ID 7-10
Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:<=0.3TbitTbitCheck (Worst of 3 Trials)172 m # Trials Run: 3 Worst Trial: Trial 1
Result Details:

Overall Summary + details of 3 worst trials
. TrialActual ValueMarginHDMIAutomationConfigData Lane ATest Frequency(MHz)Mask Moved(ps)# Acquisitions PointTbit(ps)RightJitterData(Tbit)LeftJitterData(Tbit)RightJitterData(ps)LeftJitterData(ps)Differential Swing Voltage(V)
Avg170.1 m43.33 %
StdDev3.839 m1.155 %
Range6.650 m2.000 %
Min165.7 m42.67 %
Max172.3 m44.67 %
Sum510.2 m130.0 %
Trial 1 (Worst)172 m42.7%Timing C 2D1296.7260.00016.000000000 M337.031172 m172 m58.07058.0701.064
Trial 2172 m42.7%Timing C 2D1296.7240.00016.000000000 M337.028172 m172 m58.07058.0701.048
Trial 3166 m44.7%Timing C 2D1296.6640.00016.000000000 M337.035166 m166 m55.83055.8301.057
Trial 1
Trial 1: TbitCheck
Trial 2
Trial 2: TbitCheck
Trial 3
Trial 3: TbitCheck

7-4: D1 Rise Time Reference: Test ID 7-4
Test Summary: Pass Test Description: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psTransition Time (Worst of 3 Trials)146.070 ps # Trials Run: 3 Worst Trial: Trial 2
Result Details:

Overall Summary + details of 3 worst trials
. TrialActual ValueMarginHDMIAutomationConfigTest Frequency(MHz)Data Lane AUpper Threshold(%)Lower Threshold(%)#Edge
Avg148.1 ps97.53 %
StdDev2.570 ps3.427 %
Range4.951 ps6.601 %
Min146.1 ps94.76 %
Max151.0 ps101.4 %
Sum444.4 ps292.6 %
Trial 1151.021 ps101.4%Timing C 2296.726D180.00020.00015.895000 k
Trial 2 (Worst)146.070 ps94.8%Timing C 2296.724D180.00020.00014.189000 k
Trial 3147.349 ps96.5%Timing C 2296.664D180.00020.00014.700000 k
Trial 1
Trial 1: Transition Time
Trial 2
Trial 2: Transition Time
Trial 3
Trial 3: Transition Time

7-4: D1 Fall Time Reference: Test ID 7-4
Test Summary: Pass Test Description: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psTransition Time (Worst of 3 Trials)147.491 ps # Trials Run: 3 Worst Trial: Trial 2
Result Details:

Overall Summary + details of 3 worst trials
. TrialActual ValueMarginHDMIAutomationConfigTest Frequency(MHz)Data Lane AUpper Threshold(%)Lower Threshold(%)#Edge
Avg148.3 ps97.77 %
StdDev731.9 mps975.8 m%
Range1.364 ps1.819 %
Min147.5 ps96.65 %
Max148.9 ps98.47 %
Sum445.0 ps293.3 %
Trial 1148.855 ps98.5%Timing C 2296.726D180.00020.00019.025000 k
Trial 2 (Worst)147.491 ps96.7%Timing C 2296.724D180.00020.00018.706000 k
Trial 3148.633 ps98.2%Timing C 2296.664D180.00020.00019.704000 k
Trial 1
Trial 1: Transition Time
Trial 2
Trial 2: Transition Time
Trial 3
Trial 3: Transition Time

7-10: D2 Mask Test Reference: Test ID 7-10
Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:No Mask FailuresTotal # failures (Worst of 2 Trials)0.000 # Trials Run: 2 Worst Trial: Trial 1
Result Details:

Overall Summary + details of 2 worst trials
. TrialActual ValueMarginHDMIAutomationConfigData Lane ATest Frequency(MHz)Mask Moved(ps)# Acquisitions PointTbit(ps)RightJitterData(Tbit)LeftJitterData(Tbit)RightJitterData(ps)LeftJitterData(ps)Differential Swing Voltage(V)
Avg0.00050.00 %
StdDev0.0000.000 %
Range0.0000.000 %
Min0.00050.00 %
Max0.00050.00 %
Sum0.000100.0 %
Trial 1 (Worst)0.00050.0%Timing C 2D2296.7260.00016.000000000 M337.031172 m172 m58.07058.0701.064
Trial 20.00050.0%Timing C 2D2296.7240.00016.000000000 M337.028172 m172 m58.07058.0701.048
Trial 1
Trial 1: Total # failures
Trial 2
Trial 2: Total # failures

7-10: D2 Data Jitter Reference: Test ID 7-10
Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:<=0.3TbitTbitCheck (Worst of 3 Trials)179 m # Trials Run: 3 Worst Trial: Trial 3
Result Details:

Overall Summary + details of 3 worst trials
. TrialActual ValueMarginHDMIAutomationConfigData Lane ATest Frequency(MHz)Mask Moved(ps)# Acquisitions PointTbit(ps)RightJitterData(Tbit)LeftJitterData(Tbit)RightJitterData(ps)LeftJitterData(ps)Differential Swing Voltage(V)
Avg174.5 m41.89 %
StdDev3.819 m1.347 %
Range6.616 m2.333 %
Min172.3 m40.33 %
Max178.9 m42.67 %
Sum523.5 m125.7 %
Trial 1172 m42.7%Timing C 2D2296.7260.00016.000000000 M337.031172 m172 m58.07058.0701.064
Trial 2172 m42.7%Timing C 2D2296.7240.00016.000000000 M337.028172 m172 m58.07058.0701.048
Trial 3 (Worst)179 m40.3%Timing C 2D2296.6630.00016.000000000 M337.032179 m179 m60.30060.3001.053
Trial 1
Trial 1: TbitCheck
Trial 2
Trial 2: TbitCheck
Trial 3
Trial 3: TbitCheck

7-4: D2 Rise Time Reference: Test ID 7-4
Test Summary: Pass Test Description: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psTransition Time (Worst of 3 Trials)146.844 ps # Trials Run: 3 Worst Trial: Trial 3
Result Details:

Overall Summary + details of 3 worst trials
. TrialActual ValueMarginHDMIAutomationConfigTest Frequency(MHz)Data Lane AUpper Threshold(%)Lower Threshold(%)#Edge
Avg148.4 ps97.86 %
StdDev2.005 ps2.674 %
Range3.818 ps5.091 %
Min146.8 ps95.79 %
Max150.7 ps100.9 %
Sum445.2 ps293.6 %
Trial 1150.662 ps100.9%Timing C 2296.726D280.00020.00018.253000 k
Trial 2147.690 ps96.9%Timing C 2296.724D280.00020.00014.273000 k
Trial 3 (Worst)146.844 ps95.8%Timing C 2296.663D280.00020.00018.099000 k
Trial 1
Trial 1: Transition Time
Trial 2
Trial 2: Transition Time
Trial 3
Trial 3: Transition Time

7-4: D2 Fall Time Reference: Test ID 7-4
Test Summary: Pass Test Description: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psTransition Time (Worst of 3 Trials)147.883 ps # Trials Run: 3 Worst Trial: Trial 3
Result Details:

Overall Summary + details of 3 worst trials
. TrialActual ValueMarginHDMIAutomationConfigTest Frequency(MHz)Data Lane AUpper Threshold(%)Lower Threshold(%)#Edge
Avg148.5 ps98.03 %
StdDev664.0 mps885.4 m%
Range1.325 ps1.767 %
Min147.9 ps97.18 %
Max149.2 ps98.94 %
Sum445.6 ps294.1 %
Trial 1148.467 ps98.0%Timing C 2296.726D280.00020.00016.792000 k
Trial 2149.208 ps98.9%Timing C 2296.724D280.00020.00014.622000 k
Trial 3 (Worst)147.883 ps97.2%Timing C 2296.663D280.00020.00018.031000 k
Trial 1
Trial 1: Transition Time
Trial 2
Trial 2: Transition Time
Trial 3
Trial 3: Transition Time