HDMI Test Report

Overall Results:0 of 7 Tests Failed

Test Configuration Details
Device Description
HDMI Test TypeTMDS Physical Layer Tests
HDMI Specification2.0
Test Session Details
Infiniium SW Version04.50.0008
Infiniium Model NumberDSOX93204A
Infiniium Serial NumberMY53180105
Application SW Version1.99.9025
Debug Mode UsedNo
Probe (Channel 1)Model: 1169A Serial: US44000259 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.2029E+000) Skew: Not Calibrated, Using Default Skew
Probe (Channel 2)Model: 1169A Serial: US49412951 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.2029E+000) Skew: Not Calibrated, Using Default Skew
Probe (Channel 3)Model: 1169A Serial: US44000715 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.2949E+000) Skew: Not Calibrated, Using Default Skew
Probe (Channel 4)Model: 1169A Serial: US48470614 Head: N5380A/B Atten: Not Calibrated, Using Default Atten (2.0989E+000) Skew: Not Calibrated, Using Default Skew
Last Test Date2013-09-10 14:31:58 UTC -07:00

Summary of Results

Margin Thresholds
Warning< 5 %
Critical< 2 %

Pass# Failed# TrialsTest NameWorst ActualWorst MarginSpec Range
037-10: D0 Mask Test0.00050.0 % No Mask Failures
037-10: D0 Data Jitter47 m84.3 % <=0.3Tbit
027-9: Clock Jitter31 mTbit87.6 % VALUE <= 250 mTbit
017-4: Clock Rise Time371.934 ps395.9 % VALUE >= 75.000 ps
017-4: Clock Fall Time313.966 ps318.6 % VALUE >= 75.000 ps
017-8: Clock Duty Cycle(Minimum)49.83024.6 % >=40%
017-8: Clock Duty Cycle(Maximum)50.14016.4 % <=60%


Report Detail


7-10: D0 Mask Test Reference: Test ID 7-10
Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:No Mask FailuresTotal # failures (Worst of 3 Trials)0.000 # Trials Run: 3 Worst Trial: Trial 1
Result Details:

Overall Summary + details of 3 worst trials
. TrialActual ValueMarginMaximum Margin (s)Maximum Margin (Vertical) (V)HDMIAutomationConfigEye Width(ps)Eye Height(mV)Data Lane ATest Frequency(MHz)Mask Moved(ps)# Acquisitions PointTbit(ps)RightJitterData(Tbit)LeftJitterData(Tbit)RightJitterData(ps)LeftJitterData(ps)Differential Swing Voltage(V)
Avg0.00050.00 %0.000 s0.000 V
StdDev0.0000.000 %0.000 s0.000 V
Range0.0000.000 %0.000 s0.000 V
Min0.00050.00 %0.000 s0.000 V
Max0.00050.00 %0.000 s0.000 V
Sum0.000150.0 %0.000 s0.000 V
Trial 1 (Worst)0.00050.0%0.000000000000 s0.000000000000 VNot defined1.287000 k512.910D074.1760.00016.000000000 M1.348138 k47 m45 m63.00060.000964 m
Trial 20.00050.0%0.000000000000 s0.000000000000 VNot defined1.287000 k522.580D074.1750.00016.000000000 M1.348140 k47 m45 m63.00060.000955 m
Trial 30.00050.0%0.000000000000 s0.000000000000 VNot defined1.290000 k516.130D074.1750.00016.000000000 M1.348099 k42 m45 m57.00060.000952 m
Trial 1
Trial 1: Total # failures
Trial 2
Trial 2: Total # failures
Trial 3
Trial 3: Total # failures

7-10: D0 Data Jitter Reference: Test ID 7-10
Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Test Limits:<=0.3TbitTbitCheck (Worst of 3 Trials)47 m # Trials Run: 3 Worst Trial: Trial 1
Result Details:

Overall Summary + details of 3 worst trials
. TrialActual ValueMarginHDMIAutomationConfigData Lane ATest Frequency(MHz)Mask Moved(ps)# Acquisitions PointTbit(ps)RightJitterData(Tbit)LeftJitterData(Tbit)RightJitterData(ps)LeftJitterData(ps)Differential Swing Voltage(V)
Avg45.99 m84.56 %
StdDev1.284 m384.9 m%
Range2.224 m666.7 m%
Min44.51 m84.33 %
Max46.73 m85.00 %
Sum138.0 m253.7 %
Trial 1 (Worst)47 m84.3%Not definedD074.1760.00016.000000000 M1.348138 k47 m45 m63.00060.000964 m
Trial 247 m84.3%Not definedD074.1750.00016.000000000 M1.348140 k47 m45 m63.00060.000955 m
Trial 345 m85.0%Not definedD074.1750.00016.000000000 M1.348099 k42 m45 m57.00060.000952 m
Trial 1
Trial 1: TbitCheck
Trial 2
Trial 2: TbitCheck
Trial 3
Trial 3: TbitCheck

7-9: Clock Jitter Reference: Test ID 7-9
Test Summary: Pass Test Description: 2 Channels Connection Model: TMDS differential clock jitter must not exceed 0.25*Tbit, relative to the ideal Recovery Clock. For compliance, the DUT should output 27MHz(or 25MHz), 74.25MHz, 148.5MHz, and 222.75MHz for testing.
Test Limits:<= 250 mTbitClock Jitter (Worst of 2 Trials)31 mTbit # Trials Run: 2 Worst Trial: Trial 2
Result Details:

Overall Summary + details of 2 worst trials
. TrialActual ValueMarginHDMIAutomationConfigTest Frequency(MHz)# EdgesTbit(ps)Clock Jitter(ps)
Avg30.65 mTbit87.80 %
StdDev392.4 µTbit282.8 m%
Range555.0 µTbit400.0 m%
Min30.37 mTbit87.60 %
Max30.92 mTbit88.00 %
Sum61.29 mTbit175.6 %
Trial 130 mTbit88.0%Not defined74.17816.000000000 M1.348109 k40.940
Trial 2 (Worst)31 mTbit87.6%Not defined74.17516.000000000 M1.348169 k41.690
Trial 1
Trial 1: Clock Jitter
Trial 2
Trial 2: Clock Jitter

7-4: Clock Rise Time Reference: Test ID 7-4
Test Summary: Pass Test Description: 2 Channels Connection Model: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psRaw Clock Transition Time371.934 ps
Result Details:
Result Details
HDMIAutomationConfigNot definedTest Frequency(MHz)74.178Upper Threshold(%)80.000Lower Threshold(%)20.000# Edges10.999000 k
Trial 1
Trial 1: Raw Clock Transition Time

7-4: Clock Fall Time Reference: Test ID 7-4
Test Summary: Pass Test Description: 2 Channels Connection Model: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>= 75.000 psRaw Clock Transition Time313.966 ps
Result Details:
Result Details
HDMIAutomationConfigNot definedTest Frequency(MHz)74.178Upper Threshold(%)80.000Lower Threshold(%)20.000# Edges10.999000 k
Trial 1
Trial 1: Raw Clock Transition Time

7-8: Clock Duty Cycle(Minimum) Reference: Test ID 7-8
Test Summary: Pass Test Description: 2 Channels Connection Model: Clock duty cycle must be at least 40% and not more than 60%.The Source shall meet the AC specifications in Table 4-13 across all operating conditions specified in Table 4-11. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Test Limits:>=40%Clock Duty Cycle Minimum49.830