BOARD NUMBER: N6830-26501

REVISION: B

DESIGNER NAME: LAVONNE FOGEL

ENGINEER NAME: TOM BRUHNS and RICH WILSON

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 *** Schematic ***
ATTENTION:
CES: REF_N and REF_P lost their Class1, and diff_pair_C1 property. Are routed as diff_pair_C1 but must have property readded.

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 *** Package***
Ignore following ERROR:
9100-6120 geometry sm00876 (6 pads) changed to sm01180 (5 pads).  Pin 5 was removed to reflect actual number of 5 pins, NOT 6 pins on physical part. 
Change requested by assembly shop to avoid confusion of correct placement orientation.  
Design still has the old map file and causes an ERROR message "Physical pin 5 was not found" when Saving/Backanotating in Package, this message can be IGNORED.


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 *** Librarian***
Modified geometry: sm01295 - changed "text 'ref' on layer SILKSCREEN_REFDES  >  COMPONENT_OUTLINE so 
that the reference designator showed on the ASSEMBLY DRAWING. Had sent a request to Corp. LIB but did not get 
a response to my request to change this part.

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 *** Layout ***


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 *** Fablink ***
From datum added 2 unplated holes .166 diameter at 2.375, .325 and 12.100, 4.175 to accommodate ME requirements for alignment 
to help in system assembly process.

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 *** CRITICAL NOTES ***
CES used to setup "Class" properties used in RE. DiffPairs.txt file, located in RE folder, shows class requirements.
Routing should be done in RE due to Class rules for diffpairs.
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 *** VALOR REVIEW EXCEPTION NOTES ***
Design for Assembly 

   Testpoint Analysis 
        Violation: Number of nets with not enough testpoints assigned: 1004
                        Over 330 net are N.C. or single pin connects.
                        Remaining nets are critical routed DiffPairs, engineer requested no test pads.
                        Number of nets with the right number of testpoints assigned: 612
	  Plan: Review next turn to see if testpads can be added to critical diffpairs in some locations.

   Component Analysis 
        Violation: U173 shows part violations of U138, C1143,C1348, C1349, R967, R968, C1150 - C1154. This is acceptable 
                        per M.E. due to height allowance under U173.
	  Plan: 

   Pad Stack Analysis (I) 
        Violation: PTH annular ring (4460): bga via as built per HPDL.
	  Plan: None

   Pad Stack Analysis (II) 
        Violation: 
	  Plan: 

Design for Manufacturing 

   Drill Checks 
        Violation: None
	  Plan: 

   Signal Layer Checks 1 (Outer Layer) 
        Violation: Copper area fill, built as is into HPDL part mc00650 geom, is less than 4 mils at PMH5 and PHM6.
                        Acceptable due to all are tied to DCOM (grounded).
                        Copper is less than 4 mils on PTH annular ring (4460): bga vias, as built per HPDL.
                        Copper to board edge on mounting holes for P1 and P2 (4 PL) mechanical location requirement. 
                       
        Plan: None

   Signal Layer Checks 2 (Inner Layer) 
        Violation: PTH to Copper (2112): bga vias to traces, as built per HPDL. 
                        PTH annular ring (716): bga vias, as built per HPDL.
	  Plan: None

   Power/Ground Checks 
        Violation: PTH annular ring (480): bga vias as built per HPDL.
	  Plan: None

   Solder Mask Checks  
        Violation: 
	  Plan: 

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