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HP 11835A Data Buffer![]()
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HP 11835A Specifications
Inputs(TTL Levels) Bit clock input: BNC, rear panel GPIO input: 50-pin, front panel Trigger input: BNC, rear panel Outputs(TTL Levels) Data output: BNC, front panel Clock output: BNC, front panel Program outputs: 25-pin, front panel Parallel bus outputs: 25-pin, rear panel Hop control bus: 50-pin, rear panel Programmable outputs: 3 BNCs, rear panel
Option 001 Specifications
(for use with the GSM System)Reference modes: Reference Lock, Bit Clock Lock, Frame Clock Lock, or Free Run Inputs: (rear panel BNCs) Reference: 1, 2, 5, 10, 13 MHz, > 0 dBm (50 ohms nominal) Frame clock: 216.67 Hz, TTL levels Bit clock: 270.833 kHz, TTL levels Outputs: (rear panel BNCs) 10 MHz, 13 MHz, 270.833 kHz (bit), 216.67 Hz (frame)
Option 002 Specifications
(for use with NADC or PDC systems)Reference modes: Reference Lock, Bit Clock Lock, Frame Clock Lock, or Free Run Inputs:(rear panel BNCs) Reference: 1, 2, 5, 10 MHz, > 0 dBm (50 ohms nomimal) Frame clock: 21 kHz (PDC), 24.3 kHz (NADC) TTL levels Bit colck: 42 kHz (PDC), 48.6 kHz (NADC) TTL levels Outputs:(rear panel BNCs) Reference: 10 MHz (50 ohms nominal) Symbol clock: 21 kHz (PDC), 24.3 kHz (NADC) TTL levels Bit clock: 42 kHz (PDC), 48.6 kHz (NADC) TTL levels Frame clock: 25 Hz or 50 Hz, TTL levels Note: for bit and symbol clocks, rates can be varied +/- 10 ppm.
HP 11835A Data Buffer (only one Option can be ordered) Opt 001 GSM Reference Opt 002 NADC and PDC Reference Opt 907 Front Handle Kit (5062-3988) Opt 908 Rack Mount Flange Kit (5062-3974) Opt 909 Handles w/Rack Mount Flange Kit (5062-3975)
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Page Updated: Thursday November 13 08:28:46 UTC 1997