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The HP 16522A digital pattern generator module is the perfect tool for
functional testing of your digital design. The pattern generator allows
you to check the functional characteristics of your system. See how
your system responds to unanticipated signals or clock speeds.
Correlate data captured with other modules to verify correct operation.
Use the pattern generator module in automated test environments to run
design qualification tests quickly, using only one instrument. Save
time normally spent on developing custom test hardware used for
stimulus.
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- Vectors up to 200 Bits Wide
Up to five, 40-channel
pattern generator modules can be interconnected within the modular logic
analysis system (HP 16500B) to support vectors of any width up to
200 bits with excellent channel-to-channel skew characteristics.
- Synchronized Clock Output
You can operate with either an internal or external clock. The
external clock is input via a clock pod, and has no minimum
frequency or duty cycle requirements. The internal clock is
selected as a clock period from 4 KHz to 200 MHz in steps of
250, 200, 100, 80, 50, 40, 25, 20, 10, 8, 5, etc. s or ns. A
Clock Out signal is available from the clock pod and can be used
as an edge strobe with a variable delay of up to 11 ns.
- Wait for Input Pattern
The clock pod also accepts a 3-bit input pattern. These inputs
are level-sensed so that any number of "Wait for Pattern" points
can be inserted into a stimulus program. Up to four pattern
conditions can be defined. A "Wait for IMB" can also be defined
to wait for a intermodule measurement bus event.
- Initialize Block for Repetitive Runs
The vectors in the initialize block are only output during the
first occurrence of a repetitive run. This feature is very
useful when the circuit or subsystem needs to be initialized. A
"Signal IMB" instruction can be inserted to signal other modules
to start acquisition at the time "interesting activity" is
started.
- Macros and Repeat Loops Simplify Creation of Stimulus Programs
Parameterized macros permit you to define a pattern sequence, once,
and then insert the macro by name wherever it is needed. Repeat
loops enable you to repeat a defined block of vectors a specified
number of times. A memory utilization indicator helps you track
the number of vectors contained in the stimulus program.
- ASCII Input File Format
The pattern generator module supports an ASCII file format which facilitates
connectivity to other tools in your design environment.
By generating stimulus vectors in this file format, you can read
stimulus programs into the pattern generator via a LAN
(Local Area Network) connection, via an HP-IB connection,
or via a floppy disk drive. This format has been
specifically designed for fast file transfer into the pattern generator module.
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Maxiumum Memory Depth: 258,048 vectors
Number of Output Channels at < 200 MHz clock: 20
Number of Output Channels at < 100 MHz clock: 40
Max. Number of "IF Condition" Blocks at < 50 MHz clock: 1
Max. Number of Different Macros: 100
Max. Number of Lines in a Macro: 1024
Max. Number of Parameters in a Macro: 10
Max. Number of Macro Invocations: 1,000
Max. Loop Count in a Repeat Loop: 20,000
Max. Number of Loop Invocations: 1,000
Max. Number of Wait Event Patterns: 4
Number of Input Lines to Define a Pattern: 3
Max. Number of 16522A Modules in a System: 5
Max. Width of a Vector (in a 5 Module System): 200 bits
Max. Width of a Label: 32 bits
Max. Number of Labels: 126
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HP 16522A 200M Vector/Sec Pattern Generator Module
Opt 011 TTL Clock Pod and Lead Set
Opt 012 3-State TTL/3.3 V Data Pod and Lead Set
Opt 013 3-State TTL/CMOS Data Pod and Lead Set
Opt 014 TTL Data Pod and Lead Set
Opt 021 ECL Clock Pod and Lead Set
Opt 022 ECL (terminated) Data Pod and Lead Set
Opt 023 ECL (unterminated) Data Pod and Lead Set
Opt 0B0 Delete Manual Set
Opt W03 Convert to standard 3 mo. on-site warranty
Opt W30 3 Yrs of Customer Return Repair Service
Opt W50 5 Yrs of Customer Return Repair Service
Note: Please order at least one clock pod for each HP 16522 used
as a master, and at least one data pod for every eight (8) output
channels. This typically means at least five data pods for each
HP 16522.
HP 10460A TTL Clock Pod For HP 16522A
HP 10461A 8-channel TTL Data Pod for HP 16522A
HP 10462A 8-channel 3-state TTL/CMOS Data Pod for HP 16522A
HP 10463A ECL CLock Pod HP 16522A
HP 10464A 8-channel ECL (terminated) Data Pod for HP 16522A
HP 10465A 8-channel ECL (unterminated) Data Pod for HP 16522A
HP 10466A 8-channel 3-state TTL/3.3 V Data Pod for HP 16522A
HP 10474A 8-channel Probe Lead Set for HP 16522A
HP 10347A 8-channel (50-ohm Coaxial) Probe Lead Set
HP 5090-4356 Grabbers, Surface Mount (package of 20)
HP 5959-0288 Grabbers, Through-hole (package of 20)
HP 10211A IC Probe Clip, 24-pin Dual In-Line Package
HP 10024A IC Probe Clip, 12-pin Dual In-Line Package
HP E2421A SOIC Clip Adapter Test Kit (Pomona 5514)
HP E2422A Quad Clip Adapter Test Kit (Pomona 5515)
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HP 165222A 200 M Vector/Sec Pattern Generator Module for the HP 16500P Logic Analysis System
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To help you make the
right instrument choices
Your Field Sales Engineer is ready to answer your questions about
specifications, applications and ordering. Find your Field Sales Engineer at
your Local Sales Office.
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Related HP 16500C Logic Analysis System Mainframe product datasheets:
Related product families available online:

Page Updated: Thursday November 13 07:52:23 UTC 1997