HP 16550A 102 Channel 100 MHz State/500 MHz Timing Logic Analyzer Module w/4K of acquisition memory

[ Summary ][ Features ][ Specifications ][ Key Literature ][ Ordering ][ Assistance ][ Related ]
The HP 16550A 100 MHz state and 500 MHz timing analysis module offers industry standard state and timing analysis features at an affordable price. With this module, there is no need to connect special probes to view timing activity. All channels perform either state or timing functions. Set up your analyzer to perform simultaneous, fully time-correlated state analysis on some channels and timing analysis on the rest.


[ Summary ][ Features ][ Specifications ][ Key Literature ][ Ordering ][ Assistance ][ Related ]

  • Assign channels to capture state and timing data without moving probes
  • Advanced trigger macros capture elusive problems
  • Capture up to 204, 4M deep channels simultaneously
  • Cnserve acquisition memory with transitional timing by storing samples only when data changes.
  • Enhance troubleshooting with flexible display modes

  • [ Summary ][ Features ][ Specifications ][ Key Literature ][ Ordering ][ Assistance ][ Related ]

    Probes

    Input Resistance:		100 kOhms +/- 2%
    Input Capacitance:		~8 pF
    Minimum Voltage Swing:		500 mV peak-to-peak
    Threshold Range:		+/- 6.0 V adjustable in 50 mV increments
    

    State Analysis

    Setup/Hold Time: 0/3.5ns through 3.5/0 ns adjustable in 500 ps increments Maximum State Clock Rate: 100 MHz Minimum State Clock Width: 3.5 ns Max. Time Count betw. States: 34 seconds State Clock Qualifiers: 6

    Timing Analysis

    Sample Period Accuracy:		0.01% of sample period
    Channel to Channel Skew:	2 ns, typical
    Time Interval Accuracy:		+/-(sample period + channel-to-channel skew + 0.01% of time interval reading)
    Minimum Detectable Glitch:	3.5 ns
    Maximum Timing Speed:		250 MHz, full channel/500 MHz, half channel
    

    Triggering

    Sequencer Speed:		125 MHz, maximum
    State Sequence Levels:		12
    Timing Sequence Levels:		10
    Maximum Occurrence Counter:	1,048,575
    Range Recognizers:		2
    Range Width:			32 bits each
    Timers:				2
    Timer Value Range:		400 ns to 500 seconds
    Glitch/Edge Recognizers:	2 (timing only)
    


    [ Summary ][ Features ][ Specifications ][ Key Literature ][ Ordering ][ Assistance ][ Related ]

    HP 16550A	102 Channel 100 MHz State/500 MHz Timing Logic Analyzer Module
       Opt 0B0      Delete manual set
       Opt AB0      Taiwan - Chinese localization
       Opt ABJ      Japan - Japanese localization
       Opt W03      Convert to standard 3 mo. on-site warr.
       Opt W30      3 Year Return Repair Service
       Opt W32      3 Yrs Customer Return Calibration Service
       Opt W34      3 Yrs Customer Return Stds Compliant Cal Service
       Opt W50      5 Year Return Repair Service
       Opt W52      5 Year Cust Return Calibration Service
       Opt W54      5 Year Standards Compliant Cal Service
    
    

    [ Summary ][ Features ][ Specifications ][ Key Literature ][ Ordering ][ Assistance ][ Related ]

    16550A 100 MHz State and 500 MHz Timing for the HP 16500A Logic Analysis System
    State and Timing Analysis for the HP 16500C Logic Analysis System

    If you do not have the Adobe Acrobat Reader necessary for viewing this documentation, download your Free Acrobat Reader now. Get Acrobat


    [ Summary ][ Features ][ Specifications ][ Key Literature ][ Ordering ][ Assistance ][ Related ]

    To help you make the right instrument choices

    [ Summary ][ Features ][ Specifications ][ Key Literature ][ Ordering ][ Assistance ][ Related ]


    Related HP 16500C Logic Analysis System Mainframe product datasheets:

    Related product families available online:



    Contact HP Test & Measurement. (c) Copyright 1994, 1995, 1996, 1997 Hewlett-Packard Company.

    Page Updated: Thursday November 13 07:51:14 UTC 1997