![]() | ||||
![]() |
HP 16550A 102 Channel 100 MHz State/500 MHz Timing Logic Analyzer Module w/4K of acquisition memory
| |||
![[ Summary ]](/tmo/datasheets/Graphics/tab-summary-high.gif)
![[ Features ]](/tmo/datasheets/Graphics/tab-features-reg.gif)
![[ Specifications ]](/tmo/datasheets/Graphics/tab-specs-reg.gif)
![[ Key Literature ]](/tmo/datasheets/Graphics/tab-keylit-reg.gif)
![[ Ordering ]](/tmo/datasheets/Graphics/tab-ordering-reg.gif)
![[ Assistance ]](/tmo/datasheets/Graphics/tab-assistance-reg.gif)
Probes
Input Resistance: 100 kOhms +/- 2% Input Capacitance: ~8 pF Minimum Voltage Swing: 500 mV peak-to-peak Threshold Range: +/- 6.0 V adjustable in 50 mV increments
State Analysis
Setup/Hold Time: 0/3.5ns through 3.5/0 ns adjustable in 500 ps increments Maximum State Clock Rate: 100 MHz Minimum State Clock Width: 3.5 ns Max. Time Count betw. States: 34 seconds State Clock Qualifiers: 6
Sample Period Accuracy: 0.01% of sample period Channel to Channel Skew: 2 ns, typical Time Interval Accuracy: +/-(sample period + channel-to-channel skew + 0.01% of time interval reading) Minimum Detectable Glitch: 3.5 ns Maximum Timing Speed: 250 MHz, full channel/500 MHz, half channel
Sequencer Speed: 125 MHz, maximum State Sequence Levels: 12 Timing Sequence Levels: 10 Maximum Occurrence Counter: 1,048,575 Range Recognizers: 2 Range Width: 32 bits each Timers: 2 Timer Value Range: 400 ns to 500 seconds Glitch/Edge Recognizers: 2 (timing only)
HP 16550A 102 Channel 100 MHz State/500 MHz Timing Logic Analyzer Module Opt 0B0 Delete manual set Opt AB0 Taiwan - Chinese localization Opt ABJ Japan - Japanese localization Opt W03 Convert to standard 3 mo. on-site warr. Opt W30 3 Year Return Repair Service Opt W32 3 Yrs Customer Return Calibration Service Opt W34 3 Yrs Customer Return Stds Compliant Cal Service Opt W50 5 Year Return Repair Service Opt W52 5 Year Cust Return Calibration Service Opt W54 5 Year Standards Compliant Cal Service
![[ Summary ]](/tmo/datasheets/Graphics/tab-summary-reg.gif)
![[ Features ]](/tmo/datasheets/Graphics/tab-features-reg.gif)
![[ Specifications ]](/tmo/datasheets/Graphics/tab-specs-reg.gif)
![[ Key Literature ]](/tmo/datasheets/Graphics/tab-keylit-high.gif)
![[ Ordering ]](/tmo/datasheets/Graphics/tab-ordering-reg.gif)
![[ Assistance ]](/tmo/datasheets/Graphics/tab-assistance-reg.gif)
16550A 100 MHz State and 500 MHz Timing for the HP 16500A Logic Analysis System
State and Timing Analysis for the HP 16500C Logic Analysis System
| If you do not have the Adobe Acrobat Reader necessary for viewing this documentation, download your Free Acrobat Reader now. |
|
To help you make the
right instrument choices
Related HP 16500C Logic Analysis System Mainframe product datasheets:
Related product families available online:

Page Updated: Thursday November 13 07:51:14 UTC 1997