HP 1661CP 102-Ch State/500MHz Timing Benchtop Logic Analyzer w/32-Ch 200M Vec/s Pattern Generator

The HP 1661CP 102-channel portable logic analyzer with pattern generator is the perfect tool for functional testing your digital design.

See how your system responds to specific signals or clock speeds. Correlate data captured with the state analyzer or timing analyzer to verify correct operation. Use the pattern genreator as a substitute for missing boards, integrated circuits, or buses.

[ Features ]

102 state and timing channels
100 MHz state analysis with 6 state clocks/qualifiers
Conventional timing offers resolution down to 2 ns
Transitional timing captures data bursts separated by long time periods
Integrated 32-channel 200M Vector/sec Pattern Generator with 258,048 memory depth
Stimulus synchronized to internal or external clock, with variable delay of up to 1ns
Conditional branch "IF block" of vectors at 50MHz
Macros and repeat loops
ASCII input file format, read stimulus programs via LAN

[ Specifications ]

State and Timing Channels: 102

Pattern Generator

Maximum Clock 200 MHz 100 MHz 50 MHz
Number of Data Channels 20 40 40
Memory Depth, in Vectors 258,048 258,048 258,048
"IF" Command no no yes

Timing Analysis

Conventional: 250 MHz all channels, 500 MHz, half channels
Transitional: 125 MHz all channels, 250 MHz, half channels
Glitch: 125 MHz half channels
Sample Period Accuracy: 0.01% of sample period
Channel-to-Channel Skew: 2ns, typical
Time Interval Accuracy: ±(sample period + channel-to-channel skew
+ 0.01% of time interval reading)
Min. Detectable Glitch: 3.5 ns
Memory Depth Per Channel: 4K per channel, 8K in half-channel modes

State Analysis

State Analysis Speed: 100 MHz all channels
Setup/Hold Time[1]: 0/3.5 ns through 3.5/0 ns, adjustable in 500 ps increments
Min. State Clock Width: 3.5 ns
Time Tag Resolution[2]: 8 ns or 0.1% (whichever is greater)
Max. Time Count Between States: 34 seconds
Max. State Tag Count: 4.29 X 10(9) states

Triggering

Sequencer Speed: 125 MHz, maximum
State Sequence Levels: 12
Timing Sequence Levels: 10
Max. Occurance Counter Values: 1,048,575
Pattern Recognizers: 10
Range Recognizers: 2
Range Width: 32 bits each
Timers: 2
Timer Value Range: 400 ns to 500 seconds
Glitch/Edge Recognizers: 2 (timing only)

Probes

Input Resistance: 100 kOhms, +/-2%
Input Capacitance: ~8 pF
Min. Voltage Swing: 500 mV peak-to-peak
Threshold Range: ±6.0 V, adjustable in 50 mV increments

Environmental characteristics

Net Weight: 11.8 kg (26 lbs)
Size: 218 mm H x 440 mm W x 367 mm D
(8.6 x 17.3 x 14.5 in)
Warranty: 1 year

[ Ordering ]

HP 1661CP 102-Channel 100 MHz State/500 MHz Timing Benchtop Logic Analyzer with 32-Channel Pattern Generator Opt 011 TTL Clock Pod and Lead Set (1 ea 10460A + 1 ea 10474A) Opt 012 3-State TTL/3.3V Data Pod and Lead Set (1 ea 10466A + 1 ea 10474A) Opt 013 3-State TTL/CMOS Data Pod and Lead Set (1 ea 10462A + 1 ea 10474A) Opt 014 TTL Data Pod and Lead Set (1 ea 10461A + 1 ea 10474A) Opt 021 ECL Clock Pod and Lead Set (1 ea 10463A + 1 ea 10474A) Opt 022 ECL (terminated) Data Pod and Lead Set (1 ea 10464A + 1 ea 10474A) Opt 023 ECL (unterminated) Data Pod and Lead Set (1 ea 10465A + 1 ea 10347A) Opt 0B1 Add manual set Opt 0B3 Service manual Opt 0BF Programming reference manuals Opt 1BP Mil std 45662A calibration w/ test data Opt 1CM Rackmount kit Opt ABJ Japan - Japanese localization Opt UK9 Front panel cover Opt W30 3 Yrs of Customer Return Repair Service Opt W32 3 Yrs Customer Return Calibration Service Opt W34 3 Yrs Customer Return Stds Compliant Cal Service Opt W50 5 Yrs of Customer Return Repair Service Opt W52 5 Yrs Customer Return Calibration Service Opt W54 5 Yrs Customer Return Stds Compliant Cal Service Note: For the pattern generator of HP 1660CP-series, please order at least one clock pod and at least one data pod for every eight (8) output channels.

HP 1660-Series Benchtop Logic Analyzers

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All orders include the following:

The 1661CP comes with an operating manual, mouse, and power cord.

[ Assistance ]

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