HP 71612B 12 Gb/s Error Performance Analyzer

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Accurately characterize your Gbit systems, devices and components.

The HP 71612B Error Performance Analyzer addresses applications for high speed digital testing up to 12 Gb/s, including R&D and manufacturing test of lightwave components and sub-assemblies, advanced computer technology and high-capacity communication systems.

The analyzer operates from 1 to 12 Gb/s and will operate down to 100 Mb/s with a clock-source extension. Features include high quality waveforms, versatile triggering, and sufficient memory for running multiple SONET and SDH frames at STS-192/STM-64. Use error location analysis to help identify the cause of pattern-dependent errors.

Powerful application software to speed measurement time.

The HP E4543A Q Factor and Eye Contour application software is designed to simplify the characterization of high speed optical communication links, automatically calculating the Q figure of merit.

Adaptable application software for full functional testing.

The HP E4544A OC-192/STM-64 application software automatically constructs SONET/SDH frames for functional test of network elements. Features including error and alarm generation plus CID stressing patterns.


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Except where otherwise stated, the following parameters are 
warranted performance specifications. Parameters described as 
"typical" or "nominal" are supplemental characteristics that provide 
a useful indication of typical, but non-warranted, performance 
characteristics. All specifications are for 0° to 40°C after 30 
minutes warm-up.


Test Patterns

PRBS: 2^31 - 1, 2^23 - 1, 2^15 - 1, 2^10 - 1, 2^7 - 1. User-defined pattern: Up to 8 Mbit. Zero substitution: Extends the longest run of zeroes up to pattern length less one bit on patterns 2^13, 2^11, 2^10, 2^7. Variable mark density ratio: 1/8 to 7/8 in 1/8 steps on patterns 2^13, 2^11, 2^10, 2^7. STM-64 and STS-192 patterns: Samples supplied on disk along with other stress patterns. In the pattern generator,any pattern may be split into two equal-length
patterns, with hitless switching betweenthem. The user-defined
patterns may be loaded from, or saved to, a 3½ inch, MS-DOS®
format floppy disk.

Pattern Generator

There are inputs for an external clock, external error inject,
alternate-pattern switch and data output on/off switch. There are
outputs for clock and inverted clock, data and inverted data and
pattern trigger, sub-rate (quarter-rate) clock; also four outputs
for quarter-rate data. Clock input Frequency range: 100 MHz to 12 GHz. Interface: 0.45 to 0.90 V p-p, dc coupled, 50 ohms. Clock outputs – main Frequency range: 100 MHz to 12 GHz. Interface: Complementary, dc coupled, 50 ohms, reverse terminated. (Independent control of outputs available). Amplitude: 0.5 to 2 V p-p in 10 mV steps. Range: +1.5 to -3.0 V in 10 mV steps. Data outputs – main Interface: Complementary, dc coupled, 50 ohms, reverseterminated NRZ, normal or inverted. (Independent control of outputs available). Amplitude: 0.5 to 2 V p-p in 10 mV steps. Transition times (10% to 90%): <30 ps (typical at 2 V p-p). Jitter: <20 ps p-p (typical). Range: +1.5 to -3.0 V in 10 mV steps. Clock/data delay: ±1 ns (100 MHz to 500 MHz), one clock period (500 MHz to 12 GHz). Resolution: 1 ps. Clock and data outputs – subrate Frequency range: ¼ of main clock rate. Interface: dc coupled, 50 ohms, reverse terminated. Amplitude: 0.5 to 1 V p-p in 10 mV steps. Range: 0 to -2.0 V in 10 mV steps. Trigger output: Pattern; clock/32; clock/8. Error add Internal: Single on command, or fixed ratio 1 in 10n bits,
where n = 3 to 9. External: TTL levels (active low).

Error Detector

The error detector has clock and data inputs and an input which inhibits
error counting. There are outputs for errors and pattern trigger.
The error detector has both manual and automatic setting of decision
threshold and clock/data phase alignment. Clock input Frequency range: 100 MHz to 12 GHz. Interface: 0.45 to 0.90 V p-p dc coupled, 50 ohms to 0 V or -2 V. Sensitivity: <200 mV p-p (typical at 10 Gb/s). Data input Sensitivity: <100 mV p-p (typical for 2^23 - 1 PRBS input at 10 Gb/s. 0 V high level). Impedance: 50 ohms to 0 V or -2 V, dc coupled. Decision threshold range: +1 to -3 V in 1 mV steps. Clock/data phase alignment: ±1 ns (100 MHz to 500 MHz); one clock period (500 MHz to 12 GHz). Resolution: 1 ps. Trigger output: Pattern or clock/8. Error output: 0 to -0.4 V nominal. Measurement modes: Manual, single period, repetitive period. Measurement period: 1 s to 100 days; 10, 100, 1000 errors;
107 to 1015 bits. Pattern synchronization: Automatic or manual. Selectable threshold:10-1 to 10-8. Audible output: Proportional to error ratio. Result logging: Time-stamped results to an external printer.

Clock Source

The internal clock source has a clock output and an external reference input.
It provides a variable-frequency, synthesized clock signal to the pattern
generator. See HP 70340A signal generator data sheet for full specifications. Frequency range: 1 to 20 GHz. Resolution: 1 kHz.

Measurements

Error count and ratio for: errored ones errored zeros all logic errors Errored and error-free intervals of: seconds deciseconds centiseconds milliseconds Clock frequency Error location analysis (optional) Specific bit BER Bit BER Bit error count Delta bitBER Delta biterror count Block BER Error location capture


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12 Gb/s BER Measurement and Analysis Systems
All provide mainframe, color display with integral keypad, base
unit and a set of operating and installation manuals.

HP 71612B     12 Gb/s Error Performance Analyzer

   Opt UHF    1 to 12 Gb/s error performance analyzer system
              with pattern generator and error detector

   Opt UHG    1 to 12 Gb/s system with pattern generator only
              (no error detector provided)

   Opt UHH    0.1 to 12 Gb/s system with error detector only
              (no pattern generator or clock source)

              Error location analysis

   Opt UHJ    Adds enhanced error detection to help identify
              sources of systematic errors. Do not order with
              option UHG.

             No clock source

   Opt UKC   Deletes clock source (signal generator). Do not
             order with option UHH



12 Gb/s BER Measurement and Analysis (without display and clock source)
All provide a base unit and a set of operating and installation
manuals.

If you have your own MMS display and clock source, or you wish to
build your own test bays, order only the parts you need for your
12 GHz applications.

HP 70843B     12 Gb/s Product Identification Number

   Opt UHF    0.1 to 12 Gb/s error performance analyzer with pattern
              generator and error detector

   Opt UHG    0.1 to 12 Gb/s system with pattern generator only
              (no error detector)

   Opt UHH    0.1 to 12 Gb/s system with error detector only
              (no pattern generator)

              Error location analysis

   Opt UHJ    Adds enhanced error detection to help identify
              sources of systematic errors.
Do not order with Option UHG. Accessories Opt 0B1 Extra set of manuals Opt 1CM Rack mount kit without front handles fitted Opt 0CP Rackmount kit with front handles fitted Opt +W30 Two years additional hardware support beyond the standard one-year warranty Note: If you have already purchased pattern generator-only or error detector-only units (options UHG or UHH) and wish to upgrade these to full analysis systems (option UHF), factory retrofits are available. Please contact your HP Field Engineer for further details. Hewlett-Packard manufactures the HP 71612A/HP 70843B analyzers under a quality system approved to the international standard ISO 9002 (BSI Registration Certificate No FM 10987).

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