HP E1612A 155 Mb/s Electrical Line Interface

The HP E1612A 155 Mb/s Electrical Line Interface generates and analyses ATM cell streams contained within a SONET or SDH framing format. It is a single-slot VXI module that provides test capability at the physical and ATM cell layers for the HP E4200/E4210 Broadband Series Test System.

The HP E1612A is capable of operating in both cell and SONET/SDH frame modes. This allows you to examine ATM cells mapped into a SONET/SDH frame, as well as the SONET/SDH frame data.

Line interface modules not only connect the device or system under test to your Broadband Series Test System, but also provide physical, convergence, and ATM cell testing capabilities. Transmission test capabilities include traffice generation, cell error, loss and delay measurements, traffic capture and playback.

The industry-standard HP E4200/E4210 Broadband Series Test System (BSTS) is ideal for R&D engineering, product development, field trials and quality assurance. It supports the widest variety of standard interfaces of speeds up to 622 Mb/s, the broadest, most powerful range of signalling capabilities, the industry's most complete automated conformance test suites, time-savings features for monitoring, emulation, simulation, load generation, performance and automated testing.

Line interface modules can perform physical layer testing with a minimal BSTS configuration consisting of a line interface module and chassis. Complete range of test software applications and dedicated test modules are available to perform upper layer testing.

Add the HP E4209 Cell Protocol Processor (CPP) which provides monitoring and simulation test functions at the ATM and adaptation layer by executing optional protocol testing software applications. The CPP performs many functions in hardware that are usually done in software -- such as an automatic segmentation and reassembly engine for sophisticated real-time ATM, AAL and other higher layer protocol testing.

The HP E4219A ATM Network Impairment Emulator module lets you find the limits of performance by inserting impairments into an ATM cell stream.

For complete list of BSTS Product Numbers, please refer to the Product Index page.

[ Features ]

Cell based implementation
Framing mode support for SONET or SHD
Provides physical layer measurements as well as error generation
Internal traffic generator has 1 foreground channel and up to 100 background channels
Works with Cell Protocol Processor

[ Specifications ]

Modes
Three Tx/Rx modes are available. In Terminal mode, full signal generation 
and analysis functions are available. In Repeater Mode, the received 
signal is re-transmitted (physical layer loop back). In Local Loopback 
mode, the transmit signal is electrically looped to the receiver.


ATM Cell Generation
The transmitted cell stream can contain ATM cells generated internally 
by the E1612A, and ATM cells generated by an optional E4209 Cell Protocol 
Porcessor module. ATM cells generated on-board can consist of one 
foreground channel to stimulate the channel under test, and up to one 
hundred background channels for loading purposes. Fill cells are used 
to occupy unused bandwidth.

Total Bandwidth                  
149.76 Mb/s

Modes                            
User-Network Interface (UNI) or Network-Node Interface (NNI)

HEC                              
Automatic generation

Fill Cells          
Idle or unassigned

Channel Priority Order           
Foreground, background, CPP (highest to lowest priority)

Channel Control                  
VCI
VPI
GFC
Payload Type
Cell Loss Priority

SAR-PDU Support                  
AAL-0
AAL-1


Foreground Channel
Bandwidth                        
From 100 b/s to 149.76 Mb/s in 10 b/s increments

Accuracy                         
+/- 3 b/s of selected value

Distribution                     
Off
Single burst
Periodic (according to the specified bandwidth)

Channel Depth                    
1500 cells (variable)

Cell Payload                     
Timestamp
Single cell PRBS
Cross cell PRBS
Data pattern
Byte access


Background Channels
Number of Channels              
Up to 100

Bandwidth                       
3000 b/s to 149.76 Mb/s in increments of 3000 b/s

Accuracy                        
+/- 1500 b/s of selected value

Distribution                    
Off
Periodic

Channel Density                 
Bandwidth and cell distribution for each background channel is
individually assignable up to maximum bandwidth

Channel Depth                   
16 cells

Cell Payload                    
Single cell PRBS
Data pattern
Byte access


Cell Payloads
Payloads              
Time stamp (32-bit departure time stamp value with 100 nanosecond
resolution)
Cross cell PRBS-9 
PRBS-15 (inverted and not inverted)
PRBS-23
Single cell PRBS-9
Data pattern or byte access

Data Patterns                    
User byte
AA55h or FF00h
Incrementing (value of each successive byte is incremented by 1)

Byte Access                       
Payload of all cells in the selected channel can be edited in an 
active channel environment, or off-line as a sequence of PDUs

AAL-1 automatically inserts first payload byte containing SN/SNP 
values and CSI bit


Erroring Control
Error conditions can be introduced to simulate alarm signals and 
signal stressing. Error stressing is used to generate incorrect 
bytes in a test signal.

Error Stressing Control          
Off
On
Pulse On (error condition is normally off; pulses on)
Pulse off (normally on; pulses off)
Sequence On (normally off; alternates on/off/on)
Sequence Off (normally on; alternates off/on/off)

ATM Error Injection              
Cell header or payload bytes with bit error masking

Cell Loss                       
Sequence number in the SAR-PDU is skipped and a fill cell is inserted

PRBS Error Add                   
Single bit error add to the PRBS pattern in the cell payload


SONET/SDH Stressing
SONET/SDH Stressing             
SPE pointer errors can be introduced once or at a user-defined 
sequence

Data errors can be introduced singly or at a rate of 1.0E-9 to
1.0E-3 on to the Section/RS BIP, Line/MS BIP,Path BIP, Line/MS FEBE
and Path FEBE
  
Loss of signal for either a single frame, or continuously


ATM & SONET/SDH Measurements
Measurements are sampled every 100 milliseconds and accumulated
over the user-specified measurement period. Results from the most
recent complete measurement period are retained.

Measurement Period               
Range 1 second to 3 days in resolutions of 1 second

Result Types                     
Cumulative or latched (based on most recent measurement period)

Result Formats                   
Count
Ratio
Seconds

ATM Cell Measurements            
HEC errors
Corrected headers
Cell count
Cell bandwidth
Select Cell Not Received (SCNR) alarm seconds

Cell Delay Measurements          
Cell delay
Inter-arrival time
Cell delay variation

Virtual Channel Errors           
AAL-1 SN/SNP errors
Cell loss
PRBS errors
PRBSsync loss alarm seconds

SONET/SDH Measurements          
Out of frame errors
Loss of frame alignment errors
Loss of pointer errors
Loss of cell synchronization errors
Loss of signal errors
Line AIS
Line FERF
Path AIS
Path FERF
Path yellow
Section BIP
Line BIP
Path BIP
Path FEBE
Line FEBE
Uncorrected HEC error


ATM Capture
Provides capture of 1500 cells from the selected ATM cell stream.
Capture is manual or event triggered. Manual triggering captures
1500 cells after the trigger. Event triggering captures 750 cells
pre-trigger, and 750 cells post-trigger.

Manual                          
Triggered on user request

ATM Cell Triggers              
Cell loss
Header error
PRBS error
SN/SNP byte error


SONET/SDH Capture
When in SONET/SDH frame mode, the HP E1612 line interface captures 
and displays TOH data, POH data, and path trace messages.


Front Panel Connectors and Indicators
STS-3c/STM-1 Input               
BNC connector
75ohm unbalanced input
Input gain of 0 or 20 dB

STS-3C/STM-1 Output      
BNC connector
1.0 V into 75 ohms

Receive Trigger Output           
BNC connector
TTL output

Transmit Trigger Output          
BNC connector
TTL output

Reference Clock Input 
BNC connector
10 dBm into 50 ohms
155.52 MHz with better than a 55/45% duty cycle

LED Indicators                   
Failed
Error
Access
Reference Clock
Gating
Signal
OOF
AIS
BIP
LOCS
FERF
SCNR


Applicable Standards
ATM Cells:
ITU-T Recommendation I.361 1995 B-ISDN ATM layer 
specification
 
Bellcore TA-NWT-001113 1993 Asynchronous Transfer Mode and 
ATM Adaptation Layer (AAL) Protocols Generic Requirements

SONET/SDH:
SDH as per ITU-T G.708 and I.361 for BSTS software 
releases prior to version A.10; 

SDH as per ITU-T G.707 (draft) COM 15-163-E, July 1995 Draft 
revised 

ITU-T recommendation G.707 network node interface for the
synchronous digital hierarchy (SDH) for software releases A.10 and 
later

SONET as per Bellcore TA-NWT-000253 for BSTS software 
releases prior to version A.10; 

SONET as specified by Bellcore GR-253-CORE Synchronous 
Optical Network (SONET) Transport Systems: Common Generic Criteria 
for software releases A.10 and later

PRBS Patterns:
PRBS-9 as per ITU-T O.153 1992
PRBS-23 as per ITU-T O.151 1992

EMC:
CISPR11, Class A

[ Ordering ]

HP E1612A 155 Mb/s Electrical Line Interface

Requirments: Base system requirement: HP E4200A/B HP Broadband Series Test System Form 7 Transportable Base or HP E4210A/B HP Broadband Series Test System Form 13 Mainframe Base HP E4209A/B Cell Protocol Processor HP E4219A ATM Network Impairment Emulator

All orders include the following:
User's Guide Programmer's Guide Product Release Notice

[ Key Literature ]