HP E1616A 1.5/45 Mb/s (DS1/DS3) Line Interface

The HP E1616A 1.5/45 Mb/s (DS1/DS3) Line Interface generates and analyses ATM cell streams contained within a DS1 or DS3 framing format. It is a single-slot module that provides test capability at the physical and ATM cell layers for the HP E4200/E4210 Broadband Series Test System.

It is capable of the following mappings: DS3 direct mapping as per ANSI draft T1S1/94-243, DS3 PLCP mapping as per UNI Version 3.0, DS1 direct mapping as per ITU recommendation G.804, and TDS1 PLCP mapping as per Bellcore TR-TSV-000773 Issue 1, June 1991.

Line interface modules not only connect the device or system under test to your Broadband Series Test System, but also provide physical, convergence, and ATM cell testing capabilities.

The E1616A 1.5/45 Mb/s (DS1/DS3) Line Interface can be used in conjunction with other BSTS line interfaces, dedicated test modules, and test software to perform these tests.

The industry-standard HP E4200/E4210 Broadband Series Test System (BSTS) is ideal for R&D engineering, product development, field trials and quality assurance. It supports the widest variety of standard interfaces of speeds up to 622 Mb/s, the broadest, most powerful range of signalling capabilities, the industry's most complete automated conformance test suites, time-savings features for monitoring, emulation, simulation, load generation, performance and automated testing.

Line interface modules can perform physical layer testing with a minimal BSTS configuration consisting of a line interface module and chassis.

Complete range of test software applications and dedicated test modules are available to perform upper layer testing.

Add the HP E4209 Cell Protocol Processor (CPP) provides monitoring and simulation test functions at the ATM and adaptation layer by executing optional protocol testing software applications. The CPP performs many functions in hardware that are usually done in software -- such as an automatic segmentation and reassembly engine for sophisticated real-time ATM, AAL and other higher layer protocol testing.

The HP E4219A ATM Network Impairment Emulator module lets you find the limits of performance by inserting impairments into an ATM cell stream.

[ Features ]

Cell based implementation
Selectable mode as DS1 or DS3
Selectable mapping:
- DS3 direct mapping as per ANSI draft T1S1/94-243
- DS3 PLCP mapping as per UNI Version 3.0
- DS1 direct mapping as per ITU recommendation G.804
- TDS1 PLCP mapping as per Bellcore TR-TSV-000773 Issue 1, June 1991
Provides physical layer measurements as well as error and alarm generation
Operates in Terminal, Repeater, or Physical Layer Loopback mode
Internal traffic generator has 1 foreground channel and up to 100 background channels
Works with Cell Protocol Processor

[ Specifications ]

Modes
Three Tx/Rx modes are available. In Terminal mode, full signal
generation and analysis functions are available. In Repeater mode,
the received signal is re-transmitted (physical layer loopback).
In Local Loopback mode, the transmit signal is electrically looped
to the receiver.


ATM Cell Generation
The transmitted cell stream can contain ATM cells generated internally 
by the E1616A, and ATM cells generated by an optional E4209 Cell 
Protocol Processor module. ATM cells generated on-board can consist 
of one foreground channel to stimulate the channel under test, and up 
to one hundred background channels for loading purposes. Fill cells 
are used to occupy unused bandwidth.

Total Bandwidth
DS1: 1.413 Mb/s
DS3: 40.704 Mb/s

Modes
User-Network Interface (UNI) or Network-Node Interface (NNI)
  
HEC
Automatic generation

Fill Cells
Idle or unassigned

Channel Priority Order
Foreground, background, CPP (highest to lowest priority)

Channel Control
VCI
VPI
GFC
Payload Type
Cell Loss Priority

SAR-PDU Support
AAL-0
AAL-1


Foreground Channel
Bandwidth
DS1: 100 b/s to 1.413 Mb/s
DS3: 100 b/s to 40.704 Mb/s

Accuracy
±0.02 ppm

Distribution
Off
Single burst
Periodic (according to the specified bandwidth)

Channel Depth
1500 cells (variable)

Cell Payload
Timestamp
Single cell PRBS
Cross cell PRBS
Data pattern
Byte access


Background Channels

Number of Channels            
Up to 100

Bandwidth
DS1: 3 kb/s to 1.413 Mb/s
DS3: 3 kb/s to 40.704 Mb/s

Accuracy
±10 ppm

Distribution
Off
Periodic

Channel Density
Bandwidth and cell distribution for each background channel is 
individually assignable up to maximum bandwidth

Channel Depth
16 cells

Cell Payload
Single cell PRBS
Data pattern
Byte access

 
Cell Payloads

Payloads
Timestamp (32-bit departure timestamp value with 100 nanosecond resolution)
Cross cell PRBS-9
PRBS-15 (inverted and not inverted)
PRBS-23
Single cell PRBS-9
Data pattern or byte access

Data Patterns
User byte
AA55h or FF00h
Incrementing (value of each successive byte is incremented by 1)

Byte Access
Payload of all cells in the selected channel can be edited by the 
user in an active channel environment, or off-line as a sequence of 
PDUs 

AAL-1 automatically inserts first payload byte containing SN/SNP 
values and CSI bit


Erroring Control
Error conditions can be introduced to simulate alarm signals and
signal stressing. Error stressing is used to generate incorrect
bytes in a test signal.

Error Stressing Control      
Off
On
Pulse On (error condition is normally off; pulses on)
Pulse Off (normally on; pulses off)
Sequence On (normally off; alternates on/off/on)
Sequence Off (normally on; alternates off/on/off)

ATM Error Injection
Cell header or payload bytes with bit error masking

Cell Loss
Sequence Number in the SAR-PDU is skipped and a fill cell is inserted

PRBS Error Add
Single bit error add to the PRBS pattern in the cell payload


DS1, DS3 & PLCP Stressing

DS1/PLCP Alarm Generation
AIS
Yellow

DS3/PLCP Alarm Generation
AIS
IDLE
Yellow

DS1 Error Injection
DS1 bit errors

DS3 Error Injection
F-bit invert
P-bit invert
CP-bit invert
C-bit FEBE
DS3 bit errors

PLCP Error Injection
BPI error add
FEBE generation
C1 bit masking (DS3 only)

PLCP Overhead Stressing
Normal and alternative values can be defined for overheads
Pulse or sequence controls over normal and alternative overheads


ATM, PLCP, DS1 & DS3 Measurements
Measurements are sampled every 100 milliseconds and accumulated
over the user-specified measurement period. Results from the most
recent complete measurement period are retained.

Measurement Period
Range 1 second to 3 days in resolutions of 1 second

Result Types
Cumulative or latched (based on most recent measurement period)

Result Formats
Count
Ratio
Seconds

ATM Cell Measurements
HEC errors
Corrected headers
Cell count
Cell bandwidth
Select Cell Not Received (SCNR) alarm seconds

Cell Delay Measurements
Cell delay
Inter-arrival time
Cell delay variation

Virtual Channel Errors
AAL-1 SN/SNP errors
Cell loss
PRBS errors
PRBS sync loss alarm seconds

DS1 Measurements
Code errors
CRC-6 errors
Loss of signal alarm seconds
Out-of-frame alarm seconds
AIS alarm seconds
Yellow alarm seconds
Frame count

DS3 Measurements Code errors
Parity errors
CP parity errors
FEBE errors
Loss of signal alarm seconds
Out-of-frame alarm seconds
AIS alarm seconds
IDLE alarm seconds
Yellow alarm seconds
Frame count

PLCP Measurements
BIP errors
FEBE errors
Trailer errors
OOF alarm seconds
Yellow alarm seconds
Frame count


ATM Capture
Provides capture of 1500 cells from the selected ATM cell stream.
Capture is manual or event triggered. Manual triggering captures
1500 cells after the trigger. Event triggering captures 750 cells
pre-trigger, and 750 cells post-trigger.

Manual
Triggered on user request

ATM Cell Triggers
Cell loss
Header error
PRBS error
SN/SNP byte error


PLCP Capture
Provides capture of 256 PLCP frames (overhead and ATM cell payload). 
Capture is manual or event triggered. Manual triggering captures 256 
frames after the trigger. Event triggering captures 128 frames before 
and 128 frames after trigger.

Manual
Triggered on user request

On Change
Triggered when change detected in value of selected overhead byte
Selected bits of trigger byte can be disabled

On Value
Triggered when user defined value is detected in selected overhead byte  
Any PLCP overhead byte can be selected as trigger byte

On Event
Triggered when defined PLCP event occurs (Yellow Alarm, FEBE, BIP 
Error, Trailer Error)

[ Ordering ]

HP E1616A 1.5/45 Mb/s (DS1/DS3) Line Interface

Requirements: Base system requirement: HP E4200A/B HP Broadband Series Test System Form 7 Transportable Base or HP E4210A/B HP Broadband Series Test System Form 13 Mainframe Base HP E4209A/B Cell Protocol Processor HP E4219A ATM Network Impairment Emulator

All orders include the following:
User's Guide Programmer's Guide Product Release Notice

[ Key Literature ]