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HP E1619B 25.6 Mb/s (4B/5B) Line Interface |
The HP E1619B 25.6 Mb/s Line Interface generates and analyses ATM cell streams contained within a 25.6 Mb/s (4B/5B) framing format as per the standard defined by the Desktop ATM25 Alliance. It is a single-slot module that provides test capability at the physical and ATM cell layers for the HP E4200/E4210 Broadband Series Test System.
Line interface modules not only connect the device or system under test to your Broadband Series Test System, but also provide physical, convergence, and ATM cell testing capabilities.
Three Tx/Rx modes are available. In Terminal mode, full signal generation and analysis functions are available. In Repeater mode, the received signal is re-transmitted (physical layer loopback). In Local Loopback mode, the transmit signal is electrically looped to the receiver.
For ATM cell generation, the transmitted cell stream can contain ATM cells generated internally by the E1619B, and ATM cells generated by an optional E4209B Cell Protocol Processor module. ATM cells generated on-board can consist of one foreground channel to stimulate the channel under test, and up to one hundred background channels for loading purposes. Fill cells are used to occupy unused bandwidth.
Error conditions can be introduced to simulate alarm signals and signal stressing. Error stressing is used to generate incorrect bytes in a test signal.
Cell error, loss and delay measurements are sampled every 100 ms and are accumulated over the specified measurement period. Results from the most recent complete measurement period are retained.
The HP E1619B traffic capture and playback provides capture of 1500 cells from the selected ATM cell stream. Capture is manual or event triggered. Manual triggering captures 1500 cells after the trigger. Even triggering caputres 750 cells pre-trigger, and 750 cells post- trigger.
The industry-standard HP E4200/E4210 Broadband Series Test System (BSTS) is ideal for
R&D engineering, product development, field trials and quality
assurance.It supports the widest variety of standard interfaces
of speeds up to 622 Mb/s, the broadest, most powerful range of
signalling capabilities, the industry's most complete automated
conformance test suites, time-savings features for monitoring,
emulation, simulation, load generation, performance and automated
testing.
ModesThree Tx/Rx modes are available. In Terminal mode, full signal generation and analysis functions are available. In Repeater mode, the received signal is re-transmitted (physical layer loopback). In Local Loopback mode, the transmit signal is electrically looped to the receiver.
ATM Cell GenerationThe transmitted cell stream can contain ATM cells generated internally by the E1619B, and ATM cells generated by an optional E4209B Cell Protocol Processor module. ATM cells generated on-board can consist of one foreground channel to stimulate the channel under test, and up to one hundred background channels for loading purposes. Fill cells are used to occupy unused bandwidth. Total Bandwidth 25.126 Mb/s Modes User-Network Interface (UNI) or Network-Node Interface (NNI) HEC Automatic generation Fill Cells Idleor unassigned Channel Priority Order Foreground, background, CPP (highest to lowest) Channel Control VCI VPI GFC Payload Type Cell Loss Priority SAR-PDU Support AAL-0 AAL-1
Foreground Channel Bandwidth 100 b/s to 25.126 Mb/s Accuracy +/- 0.02 ppm Distribution Off Single burst Periodic (according to the specified bandwidth) Channel Depth 1500 cells (variable) Cell Payload Timestamp Single cell PRBS Cross cell PRBS Data pattern Byte access
Background Channels Number of Channels Up to 100 Bandwidth 3 kb/s to 25.126 Mb/s Accuracy +/- 10 ppm Distribution Off Periodic Channel Density Bandwidth and cell distribution of each background channel is individually assignable up to maximum bandwidth Channel Depth 16 cells Cell Payload Single Cell PRBS Data Pattern Byte Access
Cell Payloads Payloads Timestamp (32-bit departure timestamp value with 100 ns resolution) Cross Cell PRBS-9 PRBS-15 (inverted and not inverted) PRBS-23 Single Cell PRBS-9 Data Pattern or Byte Access DataPatterns User byte AA55h or FF00h Incrementing (value of each successive byte is incremented by 1) Byte Access Payload of all cells in the selected channel can be edited by the user in an active channel environment, or off-line as a sequence of PDUs AAL-1 automatically inserts first payload byte containing SN/SNP values and CSI bit
Erroring ControlError conditions can beintroduced to simulate alarm signals and signal stressing. Error stressing is used to generate incorrect bytes in a test signal. Error Stressing Control Off On Pulse on (error condition is normally off; pulses on) Pulse off (normally on; pulses off) Sequence on (normally off; alternates on/off/on) Sequence off (normally on; alternates off/on/off) ATM Error Injection Cell header or payload bytes with bit error masking Cell Loss Sequence number in the SAR-PDU is skipped and a fill cell is inserted PRBS Error Add Single bit error add to the PRBS pattern in the cell payload
Cell Error, Loss & Delay MeasurementsMeasurements are sampled every 100 ms and accumulated over the specified measurement period. Results from the most recent complete measurement period are retained. Measurement Period Range 1 second to 3 days in resolutions of 1 second Result Types Cumulative or latched (based on most recent measurement period) Result Formats Count Ratio Seconds ATM Cell Measurements HEC errors Cell count Cell bandwidth Select Cell Not Received (SCNR) alarm seconds Cell Delay Measurements Cell delay Inter-arrival time Cell delay variation Virtual Channel Errors AAL-1 SN/SNP errors Cell loss PRBS errors PRBS sync loss alarm seconds Alarm Detection LOS (Loss OfSignal) LOPS (Loss Of PRBS Sync) SCNR (Selected Cell Not Received) X8 (Timing marker code detect)
Traffic Capture & PlaybackProvides capture of 1500 cells from the selected ATM cell stream.Capture is manual or event triggered. Manual triggering captures 1500 cells after the trigger. Event triggering captures 750 cells pre-trigger, and 750 cells post-trigger. Manual Trigger Triggered on user request ATM Cell Triggers Cell Loss Header Error PRBS Error SN/SNP Byte Error
Front Panel Connectors & Indicators 25.6Mb/s Input RJ-45connector UTP-3, 4, 5, & STP cables 100 ohm impedance (UTP), 150 ohm impedance(STP) 32 Mb/s baud rate, 25.6 Mb/s data rate 4B/5B encoding as per ATM 25.6 Mbit/s PHY Compatibility Specification 25.6 Mb/s Output RJ-45 connector UTP-3, 4, 5, & STP cables 100 ohm impedance (UTP), 150 ohm impedance (STP) 32 Mb/s baud rate, 25.6 Mb/s data rate 4B/5B encoding as per ATM 25.6 Mbit/s PHY Compatibility Specification Internal (stratum 3), External, and Recovered clock modes External Clock Input BNC connector TTL input Nominal 50 ohm impedance Trigger Output BNC connector TTL output Nominal50 ohm impedance LED Indicators Failed Error Access Gating Signal X8 SCNR Reference clock
Line interface modules can perform physical layer testing with a minimal BSTS configuration consisting of a line interface maudle and chassis. Complete range of test software applications and dedicated test modules is available to perform upper layer testing. Add the HP E4209 Cell Protocol Processor provides monitoring and simulation test functions at the ATM and adaptation layer by executing optional protocol testing software applications. The CPP performs many functions in hardware that are usually done in software -- such as an automatic segmentation and reassembly engine for sophisticated real-time ATM, AAL and other higher layer protocol testing. The HP E4219A ATM Network Impairment Emulator module lets you find the limits of performance by inserting impairments into an ATM cell stream. For complete list of BSTS Product Numbers, please refer to the Product Index page. HP E1619B 25.6 Mb/s (4B/5B) Line Interface HP E4200A/B BSTS Form-7 TransportableChassis HP E4210A/B BSTS Form-13 Mainframe Chassis HP E4209A/B Cell Protocol Processor HP E4219A ATM Network Impairment EmulatorHP E1619B 25.6 Mb/s (4B/5B) LIF
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All orders include the following:
User's Guide
Programmer's Guide
Product Release Notice
Page Updated: Thursday June 19 16:15:12 UTC 1997