HP E1695A 45 Mb/s (DS3) Line Interface

The HP E1695A 45 Mb/s (DS3) Line Interface generates and analyses ATM cell streams contained within a DS3 framing format. It is a single-slot module that provides test capability at the physical and ATM cell layers for the HP E4200/E4210 Broadband Series Test System.

Line interface modules not only connect the device or system under test to your Broadband Series Test System, but also provide physical, convergence, and ATM cell testing capabilities. Transmission test functionality includes traffic generation, cell error, loss and delay, and traffic capture and playback.

The HP E1695A provides capture of 1500 cells from the selected ATM cell stream. Capture is manual or event triggered. Manual triggering captures 1500 celss after the trigger. Even triggering captures 750 cells pre-trigger and 750 cells post-trigger. It provides capture of 256 PLCP frames (overhead and ATM cell payload). Capture is manual or event triggered. Manual triggering captures256 frames after the trigger. Event triggering captures 128 frames before and 128 frames after trigger.

The HP E4200/E4210 Broadband Series Test System (BSTS) is ideal for R&D engineering, product development, field trials and quality assurance. The industry-standard R&D performance and conformance tester that offers the most transmission and protocol technologies on a single platform, the BSTS is ideal for Frame Relay/ATM interworking testing. You can test both sides of an interworking function or device with a single BSTS since timestamps and statistics are synchronized between all modules in a BSTS chassis, allowing correlation of events and times between physical ports.

Line interface modules can perform physical layer testing with a minimal BSTS configuration consisting of a line interface module and chassis.

Complete range of test software applications and dedicated test modules are available to perform upper layer testing.

Add the HP E4209 Cell Protocol Processor provides monitoring and simulation test functions at the ATM and adaptation layer by executing optional protocol testing software applications. The CPP performs many functions in hardware that are usually done in software -- such as an automatic segmentation and reassembly engine for sophisticated real-time ATM, AAL and other higher layer protocol testing.

The HP E4219A ATM Network Impairment Emulator module lets you find the limits of performance by inserting impairments into an ATM cell stream.

For complete list of BSTS Product Numbers, please refer to the Product Index page.

[ Features ]

Cell based implementation with support for ATM or SMDS
PLCP Mapping
Framing formats supported: M23 and C-bit parity
Operates in Terminal, Repeater, or Near-end Loopback modes
Provides physical layer measurements as well as error and alarm generation
Internal traffic generator has 1 foreground channel and up to 100 background channels
Works with Cell Protocol Processor

[ Specifications ]

Modes
Three Tx/Rx modes are available. In Terminal mode, full signal 
generation and analysis functions are available. In Repeater mode, 
the received signal is re-transmitted (physical layer loopback). In 
Local Loopback mode, the transmit signal is electrically looped to 
the receiver.


ATM Cell Generation
The transmitted cell stream can contain ATM cells generated
internally by the E1695A, and ATM cells generated by an optional
HP E4209B Cell Protocol Processor module. ATM cells generated on-board
can consist of one foreground channel to stimulate the channel under 
test, and up to one hundred background channels for loading purposes. 
Fill cells are used to occupy unused bandwidth.

Total Bandwidth
40.704 Mb/s

Modes
User-Network Interface (UNI) or Network-Node Interface (NNI)

HEC
Automatic generation

Fill Cells
Idle or unassigned

Channel Priority Order
Foreground, background, CPP (highest tolowest priority)

Channel Control
VCI
VPI
GFC
Payload Type
Cell Loss Priority

SAR-PDU Support
AAL-0
AAL-1


Foreground Channel

Bandwidth
100 b/s to 40.704 Mb/s

Accuracy
±0.02 ppm

Distribution
Off
Single Burst
Periodic (according to the specified bandwidth)

Channel Depth
1500 cells (variable)

Cell Payload
Timestamp
Single cell PRBS
Cross cell PRBS
Data pattern
Byte access


Background Channels

Number of Channels
Up to 100

Bandwidth
3 kb/s to 40.704 Mb/s

Accuracy
±10 ppm

Distribution
Off
Periodic

Channel Density
Bandwidth and cell distribution for each background channel is
individually assignable up to maximum bandwidth

Channel Depth
16 cells

Cell Payload
Single cell PRBS
Data pattern
Byte access


Cell Payloads

Payloads
Timestamp (32-bit departure timestamp value with 100 nanosecond 
resolution)

Cross Cell
PRBS-9
PRBS-15 (inverted and not inverted)
PRBS-23
Single Cell PRBS-9
Data Pattern or Byte Access

Data Patterns
User byte
AA55h or FF00h
Incrementing (value of each successive byte is incremented by 1)

Byte Access
Payload of all cells in the selected channel can be edited by the user 
in an active channel environment, or off-line as a sequence of PDUs
                                 
AAL-1 automatically inserts first payload byte containing SN/SNP 
values and CSI bit


ATM Erroring Control
Error conditions can be introduced to simulate alarm signals and
signal stressing. Error stressing is used to generate incorrect
bytes in a test signal.

Error Stressing Control
Off
On
Pulse On (error condition is normally off; pulses on)
Pulse off (normally on; pulses off)
Sequence On (normally off; alternates on/off/on)
Sequence Off (normally on; alternates off/on/off)

ATM Error Injection
Cell header or payload bytes with bit error masking

Cell Loss
Sequence Number in the SAR-PDU is skipped and a fill cell is inserted

PRBS Error Add
Single bit error add to the PRBS pattern in the cell payload


DS3/PLCP Stressing

DS3/PLCP Alarm Generation
AIS
Idle
Yellow

DS3Error Injection
F-bit invert
P-bit invert
CP-bit invert
C-bit FEBE
DS3 bit errors

PLCP Error Injection
BIP error add
FEBE generation
C1 bit masking

PLCP Overhead Stressing
Normal and alternative values can be defined for overheads
Pulse or sequence control of normal and alternative overheads


ATM, PLCP & DS3 Measurements
Measurements are sampled every 100 milliseconds and accumulated over 
the user-specified measurement period. Results from the most recent 
complete measurement period are retained.

Measurement Period
Range 1 second to 3 days in resolutions of 1 second

Result Types
Cumulative or latched (based on most recent measurement period)

Result Formats
Count
Ratio
Seconds

ATM Cell Measurements
HEC errors
Cell count
Cell bandwidth
Select Cell Not Received (SCNR) alarm seconds

Cell Delay Measurements
Cell delay
Inter-arrival time
Cell delay variation

Virtual Channel Errors
AAL-1 SN/SNP errors
Cell loss
PRBS errors
PRBS sync loss alarm seconds

DS3 Measurements
Code errors
Parity errors
CP parity errors
FEBE errors
Loss of signal alarm seconds
Out-of-frame alarm seconds
AIS alarm seconds
IDLE alarm seconds
Yellow alarm seconds
Frame count

PLCP Measurements
BIP errors
FEBE errors
Trailer errors
OOF alarm seconds
Yellow alarm seconds
Frame count


4.1  ATM Capture
Provides capture of 1500 cells from the selected ATM cell stream.
Capture is manual or event triggered. Manual triggering captures
1500 cells after the trigger. Event triggering captures 750 cells
pre-trigger, and 750 cells post-trigger.

Manual
Triggered on user request

ATM Cell Triggers
Cell loss
Header error
PRBS error
SN/SNP byte error


PLCP Capture
Provides capture of 256 PLCP frames (overhead and ATM cell payload). 
Capture is manual or event triggered. Manual triggering captures 256 
frames after the trigger. Event triggering captures 128 frames before 
and 128 frames after trigger.

Manual
Triggered on user request

On Change
Triggered when change detected in value of selected overhead byte
Selected bits of trigger byte can be disabled

On Value
Triggered when user defined value is detected in selected overhead byte  
Any PLCP overhead byte can be selected as trigger byte

On Event
Triggered when defined PLCP event occurs (Yellow Alarm, FEBE, BIP
Error, Trailer Error)


Front Panel Connectors & Indicators

DS3 Input
BNC connector
75 ohm impedance
44.736 Mb/s
B3ZS code
0 dB or -20 dB relative to High, X connect, and Low levels

DS3 Output
BNC connector
75 ohm impedance
44.736 Mb/s
B3ZS code
Peak voltage may be set to High (850 mV), connect (710mV), and
Low (300 mV) transmit levels
Internal (stratum 3), External, and Recovered clock modes

External Clock Input
BNC connector
TTL input
Nominal 50 ohm impedance

Trigger Output
BNC connector
TTL output
Nominal 50 ohm impedance

LED Indicators
Failed
Error
Access
Gating
Signal
OOF
AIS
BIP
Yellow
SCNR
Reference Clock

[ Ordering ]

HP E1695A 45 Mb/s (DS3) Line Interface

Requirements: Base system requirement: HP E4200A/B HP Broadband Series Test System Form 7 Transportable Base or HP E4210A/B HP Broadband Series Test System Form 13 Mainframe Base HP E4209A/B Cell Protocol Processor HP E4219A ATM Network Impairment Emulator

All orders include the following:
User's Guide Programmer's Guide Product Release Notice

[ Key Literature ]