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HP E2412A Intel i860XP Preprocessor Interface |
The HP E2412A provides an easy way to connect your Intel i860XP
target system to an HP logic analyzer. The preprocessor
provides a complete electrical and mechanical interface between
your target system and an HP logic analyzer. Included with the E2412A
is software which automatically configures the analyzer labeling
address, data, and status lines. The inverse assembler decodes bus
activity and displays i860XP mnemonics in state listings.
Microprocessor Compatibility
262 pin PGA up to 50 MHz Intel i860XP
Logic Analyzers Supported
HP 16540A/D, 16541A/D HP 16542A HP 16550A HP 1655XA HP 1660A/AS, C/CS
Probes Required
Nine 16-channel probes are required for complete state disassembly and to monitor all signals.
Adapters
All pods are terminated on the probe. No additional TAs need to be ordered.
Signal Line Loading
Two CMOS inputs plus 3 pF maximum on the ADS# line Three CMOS inputs plus 3 pF maximum on the HITM# line One CMOS input, one TTL input plus 3 pF maximum on the WB/WT# line Two CMOS inputs and one TTL input plus 3 pF maximum on the KEN# line One CMOS input plus 100 kohm on Endian and StPrCk One CMOS input plus 3 pF maximum on all other lines
Environmental
Temperature Operating 0o to +55o C (+32o to +131o F) Nonoperating -40o to +75o C (-40o to +16o F) Humidity Up to 90% noncondensing. Avoid sudden extreme temperature changes which could cause condensation within the instrument Altitude Operating 4,600 m (15,000 ft) Nonoperating 15,300 m (50,000 ft)
Additional Characteristics:
Operations Displayed: Special Cycle I/O Read/Write Code Read Data Read/Write Normal Read Pipelined Load Page Directory Read/Write Page Table Read/Write Write Through Store Miss Write Back Target Signal Timing Meets all timing specifications in the i860XP data book except the following: 10 ns setup for NA# 9 ns setup for BRDY# and KEN# 6 ns hold for A5 - A31 during BOFF#-initiated inquire cycles
HP E2412A Intel i860XP Preprocessor Interface
Page Updated: Thursday June 19 16:11:40 UTC 1997