HP E2432A Intel 80960CA/CF Preprocessor Interface

Product Summary

The HP E2432A preprocessor interface for the Intel 80960CA/CF is a mechanical and electrical interface between the Intel 80960CA/CF and various HP logic analyzers for real-time state analysis. The preprocessor routes signals; matches analyzer and chip setup and hold times; aligns address, data and status signals; and filters non-data transfers such as idle and wait states.

Preprocessor software configures the logic analyzer labeling address, data and status lines. Additionally, when a state trace is displayed, 80960 mnemonics are listed, providing easy correlation between the data captured and the controlling program.

Product Features

• Supports operation in pipelined bus mode
  The HP E2432A provides circuitry to align the data, address and status signals during pipelined bus cycles so the pipeline skew is transparent to the user.
• Filters out unwanted states
  The HP E2432A filters states so that only valid data transfers get clocked in to the logic analyzer. Wait, idle and other states when the processor is not the bus master, do not get passed to the analyzer. This ensures optimal use of the analyzer's acquisition memory.
• Allows user to see when processor relinquishes control of the bus
  The initial state of a HOLDA or BOFF# transaction is recorded. Logic analyzer time tags can be used to measure the duration of these transactions.
• Supports configuration in all memory regions
  The HP E2432A supports the six/seven items configurable in each of the 80960CA/CF bus's 16 different memoryregions: wait states, READY#/BTERM# enabling, bursting, pipelining, bus size, byte ordering and/or cache definition ability.
• Monitors all 80960CA/CF signals of interest including the on-chip interrupt and DMA controllers

Product Specifications

Microprocessor Compatibility
168 pin PGA Intel 80960CA/CF 40 MHz

Logic Analyzers Supported
HP 1650, 1652, 16510, 1654
HP 16540 A/D and 16541A/D
HP 16542 
HP 16554A, 16555A, 16556A
HP 1660C, 1661C

Pods Required
Five pods are required for inverse assembly.  Two extra pods 
can be added to provide visibility of the on-chip interrupt 
controller and DMA controller signals.

Adapters
No adapters are required

Signal Line Loading
One 74FCT load : PCLK1, PCLK2, A28, A29, A30
No load : DT/R#, CLKIN CLKMODE
One 74F load : all other signals
All Vss lines are tied together
All Vcc an NC lines are left open

Product Ordering Information

HP E2432A	Intel 80960CA/CF Preprocessor Interface

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