HP E2443B Intel Pentium® 510/60 MHz and 567/66 MHz Preprocessor Interface

Product Summary

The Pentium preprocessor interface has four modes of operations. In the state-per-transfer mode, the logic analyzer is clocked upon completing data transfer cycles. In this mode, the preprocessor keeps track of the address pipeline and aligns data with its parent address. Additionally, activity during an HLDA or BOFF# assertion is captured.

In the state-per-clock mode, data is captured on every system clock, so you see all processor activity including wait and idle states. This mode of operation is useful in finding memory locations that do not respond with data and in checking memory control systems.

In the timing analysis mode, all signals are buffered, but otherwise pass straight through to the logic analyzer.

The debugger mode is identical to state-per-transfer mode, except that whenever IU, IV or IBT are asserted, data is captured regardless of whether or not it is valid.

Product Features

• The logic analyzer captures all bus cycles, including prefetches, and marks unexecuted prefetches.
• Disassembly of floating point instructions is supported.
• Burst mode addresses are calculated and displayed in the state trace listing.
• Timing analysis is supported; all signals go through 6.4 ns maximum buffers.
• State-per-clock mode runs up to 100 MHz providing margin for testing.
• Preprocessor can be configured to prequalify the logic analyzer clock on BRDY#, ADS#, EADS#, BOFF# and HLDA, saving logic analyzer resources.

Product Specifications

Microprocessor Compatibility
Pentium processor 510/60 MHz CPU 273-pin PGA 
Pentium processor 567/66 MHz CPU 273-pin PGA 

Logic Analyzers Supported
HP 16540 A/D and 16541A/D
HP 16554A, 16555A, 16556A
HP 1660C, 1661C, 1662C, 1663C, 1664C

Pods Required
Eight 16-channel pods are required for inverse assembly.  Two additional 
pods provide monitoring of other status signals.

Adapters
All ten pods are terminated on the preprocessor.  No additional termination 
adapters are required.

Signal Line Loading
7 pF in series with 100 ohms on CLK
14 pF in series with 50 homs on ADS#, BOFF#, BRDY#, BRDYC#, HDLA, KEN# 
and W/R#
14 pF on IU, IV, IBT, INIT, TCDO, SMIACT#, R/S# and RESET
10 pF on all other signals

Product Ordering Information

HP E2443B	Intel Pentium &trade at iCOMP Index 510/60 MHz and 567/66 MHz Preprocessor Interface

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All orders include the following:

Configuration software

Inverse assembler

To help you make the right instrument choices

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