HP E2448A Motorola 68360 (QUICC) Preprocessor Interface

Product Summary

The HP E2448A preprocessor interface provides an easy way to connect an HP logic analyzer to a target system using the Motorola 68630 (QUICC) microprocessor. For example, all necessary clocks are passed through by the preprocessor to the logic analyzer, ensuring that data is captured at the correct time.

Included with the preprocessor are configuration files which automatically label address, data and status lines, allowing end users to get started quickly. In addition to the configuration files, an inverse assembler is included which disassembles state listings presenting the information in 68360 microprocessor mnemonics.

Product Features

• Instructions that are pre-fetched, but not executed, are marked in the trace display
• 10-pin Background Debug Mode (BDM) connector provides connection to a BDM debugger
• Target signal timing is adjustable from 3.5 ns setup/0 s hold to 0 s setup/3.5 ns hold
• Displays the following operations:
  • All cycles with AS asserted
  • All cycles with DS asserted
  • All show cycles (address and data)

Product Specifications

Microprocessor Compatibility
Up to 33 MHz, 241 pin PGA 68360A
Up to 33 MHz, 240 pin PQFP 68360A

Logic Analyzers Supported
HP 16550A
HP 16554A, 16555A, 16556A
HP 1661A/C

Pods Required
The preprocessor uses 11 pods.  Six are required for inverse assembly.
An additional five are provided for state and timing analysis of 
additional signals on the microprocessor.

Adapters
No adapters are required

Signal Line Loading
25 pF in parallel with 100 kOhms to Vss for AS, DS, CLK01
25 pF in parallel with 10 kOhms to Vdd for FREEZE BCLR0, RMC, TRIS, 
MODCK1, MODCK0
15 pF in parallel with 100 Kohms to Vss for all others

Product Ordering Information

HP E2448A	Motorola 68360 (QUICC) Preprocessor Interface

 

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Page Updated: Tuesday February 04 02:39:28 UTC 1997