HP E2449B PowerPC Inverse Assembler

Product Summary

The HP E2449B inverse assembler supports several versions of the Motorola and IBM PowerPC families.

The software configures the logic analyzer, labeling address, data, and status lines. Additionally, when a state trace is displayed, the data is disassembled and listed in the appropriate PowerPC mnemonics.

Product Features

State-per-address or data cycle mode, the logic analyzer records only those states in which one or more of the strobes are asserted. These strobes include AACK, ARTRY, TA, DRTRY, and TEA for the PowerPC 601/603; IOTV (TS6) for the IBM PowerPC 403GA. This mode filters wait states and exposes the PowerPC's decoupled address and data buses.

• State-per-clock mode, address and data are captured on each CPU clock. This feature is useful in hardware validation and debugging of system crashes.

• Timing mode, all address, data, and status lines are labeled on the logic analyzer display when making accurate timing measurements.

• inverse assembler supports all processor instructions. In addition, disassembly is synchronized at branch addresses.

Product Specifications

Microprocessor Compatibility

The Motorola/IBM PowerPC 601 and 603 are supported. The IBM 403GA is also supported.

Microprocessor Speed

Maximum state analysis speeds are determined by the logic analyzer used. The HP 16550A is rated at 100MHz, the HP 16554A at 70 MHz, the HP 16555A at 110 MHz, the HP 16556A at 100 MHz, and the HP 1660-series at 100MHz. No hardware is supplied with this product.

Logic Analyzers Supported

Number of Probes Required

Target Signal Timing

Data must be valid for a 3.5 ns window with respect to the logic analyzer clock, which strobes bits into the logic analyzer on the rising edge.

For the PowerPC 601, if BCLK_EN is used to pace the bus at a fraction of the microprocessor clock, then BCLK_EN=0 should be ANDed with the storage qualification term. This process is discussed in detail in the User's Guide.

Termination Required

You are responsible for providing a connection and termination scheme for the logic analyzer probes. Several techniques are discussed in the application note Minimizing Intrusion Effects When Probing With A Logic Analyzer, publication number 5962-8920E, available from the nearest HP Sales Office.

Evaluation board compatibility

The IBM Microelectronics' PowerPC 403GA Evaluation Board, which includes 20-pin termination headers for an HP logic analyzer, is supported by the 403GA configuration file of the HP E2449B.

Product Ordering Information

HP E2449B       PowerPC Inverse Assembler

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Configuration software

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