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HP E2464A Intel 80960J-Series (i960) Preprocessor Interface
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![[ Summary ]](../Graphics/tab-summary.gif)
![[ Features ]](../Graphics/tab-features.gif)
![[ Specifications ]](../Graphics/tab-specs.gif)
![[ Ordering ]](../Graphics/tab-ordering.gif)
Product Summary
The HP E2464A preprocessor interface provides an easy way to connect an HP logic analyzer to a target system using the Intel 80960J-series microprocessors.
![[ Summary ]](../Graphics/tab-summary.gif)
![[ Features ]](../Graphics/tab-features.gif)
![[ Specifications ]](../Graphics/tab-specs.gif)
![[ Ordering ]](../Graphics/tab-ordering.gif)
Product Features
- All necessary clocks are passed through by the preprocessor to the logic analyzer to ensure that data is captured at the correct time.
- Software is shipped with the product that automatically configures the logic analyzer and generates labels for address, data, and status signals.
- The included disassembler displays execution traces in 80960J-series microcontroller mnemonics.
- Instructions which are pre-fetched but not executed are marked in the trace display.
- Supports both 5V and 3.3V target systems
- Three modes of operation are available: State-per-transfer (filters out wait and idle states, State-per-clock (provides a complete display of all bus activity), and Timing analysis(up to 500 MHz; channel-to-channel skew: 1 ns)
![[ Summary ]](../Graphics/tab-summary.gif)
![[ Features ]](../Graphics/tab-features.gif)
![[ Specifications ]](../Graphics/tab-specs.gif)
![[ Ordering ]](../Graphics/tab-ordering.gif)
Product Specifications
Microprocessors Supported
Description | Bus Clock |
132 pin PGA 80L960JA 3.3 V | 40 and 50 MHz |
132 pin PGA 80960JD 5.0 V | 40 and 50 MHz |
132 pin PGA 80960JF 5.0 V | 40 and 50 MHz |
132 pin PGA 80L960JF 3.3 V | 40 and 50 MHz |
Logic Analyzers Supported
- HP 1650A/52A
- HP 1660A/61A
- HP 1660AS/61AS (with oscilloscope)
- HP 16500
16500 Cards Supported:
- HP 16510B
- HP 16511B
- HP 16540A/41A/42A
- HP 16550A (one- or two- card)
- HP 16554A/55A (two- or three- card)
Pods Required
Five pods must be used for disassembly. An additional pod may be added to allow timing measurements of all processor signals.
Termination Adapters (TAs)
All pods are terminated on the probe. No additional Termination Adapters need to be ordered.
Optional Adapters
For PQFP target systems, the HP E5337A option is required.
Signal Line Loading
- 16pF on DEN#, RESET# and RDYRCV#
- 8 pF on all other signals
![[ Summary ]](../Graphics/tab-summary.gif)
![[ Features ]](../Graphics/tab-features.gif)
![[ Specifications ]](../Graphics/tab-specs.gif)
![[ Ordering ]](../Graphics/tab-ordering.gif)
Product Ordering Information
HP E2464A Intel 80960J-Series (i960) Preprocessor Interface
HP E5337A Intel 80960J-Series 132-pin PQFP adapter
The HP 16500C Logic Analysis System Mainframe and HP 16501 Expansion Frame
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![[ Summary ]](../Graphics/tab-summary.gif)
![[ Features ]](../Graphics/tab-features.gif)
![[ Specifications ]](../Graphics/tab-specs.gif)
![[ Ordering ]](../Graphics/tab-ordering.gif)
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Page Updated: Thursday June 19 16:12:47 UTC 1997