HP E2466B Intel Pentium® Pro Preprocessor Interface


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Product Summary

The HP E2466B preprocessor interface for the PentiumŪ Pro processor allows you to easily trace the operation of a PentiumŪ Pro processor system. The preprocessor and its transaction tracker software for the HP 16500B logic analysis system simplify the analysis of the PentiumŪ Pro multi processor bus. Bus transactions are summarized in the state listing display for rapid interpretation of bus operation. Bus timing diagrams displayed as waveforms are overlaid with status information for quickly indentifying bus conditions.



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Product Features



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Product Specifications

Microprocessor Compatibility

387 pin SPGA PentiumŪ Pro Processors 66 MHz Maximum Bus Clock Rate

Logic Analyzers Supported

HP 16550A HP 16554A HP 16555A/D HP 16556A/D

Pods Required

10 pods are required for complete analysis

Adapters

All pods are terminated on the probe. No additional TAs need to be ordered.

Signal Line Loading

1 pF in parallel with 1.6 kohms on CLK input 1 pf in parallel with 490 ohms on GTL+ inputs 1 pF shunted by 250 ohms in series with 10 kohms shunted by 10 pf on 3.3V Tolerant, APIC, and JTAG inputs

Additional Characteristics:

Transaction tracker bus phase displays Request Phase Snoop Phase Error Phase Response Phase Data Phase Summary Information (transaction timing measured in bus clocks) Agents ADS#, DID[7:0], (Ab[23:16]#) Symmetric 1: Show/Suppress Symmetric 2: Show/Suppress Symmetric 3: Show/Suppress Symmetric 4: Show/Suppress Priority: Show/Suppress Transaction Types ADS#, REQa[4:0]#, REQb[4:0]# Deferred Replies: Show/Suppress Interupt Acknowledge: Show/Suppress Special Transactions: Show/Suppress Branch Trace Messages: Show/Suppress I/O Reads: Show/Suppress I/O Writes: Show/Suppress Memory Read and Invalidate: Show/Suppress Memory Reads - Data: Show/Suppress Memory Reads - Code: Show/Suppress Memory Writes: Show/Suppress Memory Writebacks: Show/Suppress Note: Agents and transaction type filter terms are combined in display by "ANDing" Clock qualification Expanded mode: Enables logic analyzer clocking while transactions are outstanding on the Pentium Pro bus Compacted mode: Maximizes logic analyzer utilization by only enabling clocking during transaction phases and transfer of reset configuration information on the PentiumŪ Pro bus



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Product Ordering Information

HP E2466B	PentiumŪ Pro preprocessor interface 
		(requires HP 16500B mainframe)

HP 16500B/C	Logic Analysis System Mainframe

HP 16500U	Upgrades HP 16500A mainframe to 16500B mainframe

HP 16550A	100 MHz state/500 MHz timing logic analyzer module
		(requires HP 16500B mainframe)

HP 16554A 	500 K Sample, 70 MHz state/250 MHz timing logic analyzer module
		(requires HP 16500B mainframe)

HP 16555A	1 M Sample, 110 MHz state/500 MHz timing logic analyzer module
		(requires HP 16500B mainframe)

HP 16555D	2 M Sample, 110 MHz state/500 MHz timing logic analyzer module
		(requires HP 16500B mainframe)

HP 16556A	1 M Sample, 100 MHz state/400 MHz timing logic analyzer module
		(requires HP 16500B mainframe)

HP 16556D	2 M Sample, 100 MHz state/400 MHz timing logic analyzer module
		(requires HP 16500B mainframe)

HP 10390A	System Performance Analysis Software

   Opt 004	For HP 16550A

   Opt 006	For HP 16554A, 16555A, 16556A

HP B4600A	System Performance Analysis Software
		(requires HP 16505A prototype analyzer)

HP E2466B Preprocessor Interface for the Intel Pentium Pro

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