HP E2473A Intel i960H-Series Preprocessor Interface

Product Summary

The HP E2473A preprocessor for the Intel i960H series is a mechanical and electrical interface between the Intel i960H series and various HP logic analyzers for real-time state analysis. The preprocessor routes signals, aligns address, data and status signals, and filter non-data transfers such as idle and wait states.

Preprocessor software configures the logic analyzer labeling address, data, and status lines. Additionally, when a state trace is displayed, i960 mnemonics are listed, providing data captured and the controlling program.

Product Features

• Supports timing, state-per-clock and state-per transfer operating modes
  • Timing Mode: buffers i960H series signals and passes them on to the logic analyzer

  • State-Per-Clock Mode: All valid data transfers on the i960H series bus clock data into the logic analyzer

  • State-Per-Transfer Mode: Aligns address, status and data before clocking the logic analyzer; deskews the pipelined bus of the processor.

• Filters states so that only valid data transfers (instruction fetches,cache fills data reads and writes) get clocked into the analyzer.
  Wait states, idle states (that is, states when there are no valid data on the bus) do not get passed on to the analyzer. This ensures optimal use of the analyzer's acquisition memory. Logic analyzer time tags can be used to measure the duration of the transactions from state to state.

• Displays or suppresses selected i960 instructions
  These include unexecuted prefetches, jumps, calls/returns and other instructions. In addition, memory read/write cycles can be displayed or suppressed.

• Monitors all i960H series signals of interest, including the on-chip interrupt and DMA controllers
  

Product Specifications

Microprocessor Compatibility
168-pin Intel 80960HA, 80960HD and 80960HT 3.3 V microprocessors
168-pin Intel 80960HA, 80960HD and 80960HT 5.0 V microprocessors
(Also, all other processors made by other manufacturers that comply with the 
Intel i960H series specification)

Logic Analyzers Supported
HP 1660A/AS, C/CS
HP 1661A/AS, C/CS
HP 1670A
HP 1671A
HP 1655XA

Pods Required
Six 17-channel pods are required for inverse assembly.  An additional pod 
is required to monitor all i960 signals.

Adapters
All pods are terminated on the probe. No additional TAs need to be ordered.

Signal Line Loading
~16 pF on ADS#, RESET#, BLAST#, A2, CT0CT1, READY#, BTERM#, WAIT# and BE[2:0]
~8 pF on all other signals

Additional Characteristics:
Timing Analysis
The following signals have 1 ns channel-to-channel skew in timing analysis:
DATA[31:0], BTERM#, BLAST#, RESET#, WAIT, NMI, ONCE#, HOLD, HOLDA, BOFF#, BREQ, 
BSTALL, FAIL#, READY#, STEST, PCHK#, DP[3:0], XINT[7:0], DT/R#, DEN#, VOLDET, 
TRST#, TDE, TDO, TMS

The follwing signals are sampled only once (in state and timing mode) for 
each rising edge of the CPU clock:  A[31:0], W/R#, D/C#, SUP#, ADS#, LOCK#, 
BE[3:0], CT[3:0]

Microprocessor Clock Speed	
40 MHz with 1X core (40 MHz internal)
33 MHz with 2X core (66 MHz internal)
25 MHz with 3X core (75 MHz internal)
Minimum clock speed supported is 5 MHz

Environmental
Temperature	0o to +50o C (+32o to +131o F)
Altitude	4,600 m	  50,000 ft
Humidity	Up to 75% noncondensing.  Avoid sudden, extreme temperature which could cause 
		condensation on the circuit board.

Product Ordering Information

HP E2473A	Intel i960H Series Preprocessor Interface

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