HP E2925A 33 MHz, 32 Bit PCI Exerciser and Analyzer

The HP E2925A PCI Exerciser and Analyzer card is a fully programmable PCI master and target with an on-board PCI state logic analyzer, a PCI protocol observer and built-in test functions.

It is a powerful tool to accelerate the development of PCI devices and systems significantly, and ensure exhaustive verification at the earliest opportunity. The PCI Exerciser and Analyer hardware provides together with the Graphical User Interfaces (GUI) based on Windows^® 95/NT an interactive instrument that can be used by engineers throughout the whole PCI developement process of chips, cards, and systems.

With its C-Application Programming Interface (C-API), the fully in-system programmable HP E2925A 32 bit, 33 MHz PCI Exerciser and Analyzer card can also be completely integrated into your test environment for validating your PCI based design.

Additional hardware and software modules (GUIs) allow you to tailor the HP E2925A PCI Exerciser and Analyzer card to your specific application needs.

The HP E2970A PCI Analyzer Graphical User Interface for Windows 95 and Windows NT is a comprehensive graphical user interface for the HP E2925A's on board PCI state logic analyzer.
The HP E2971A PCI Exerciser Graphical User Interface for Windows 95 and Windows NT is a comprehensive graphical user interface for the HP E2925A's programmable PCI master and target exerciser.
The HP E2972A PCI Performance Analyzer is a comprehensive graphical user interface based on Windows 95 and Windows NT for the HP E2925A to evaluate and analyze PCI system performance in depth, so that PCI systems and componets are optimized.
The HP E2974A Sub-System Stress Tests is a library of ready to run tests based on Windows 95 and Windows NT to stress PC systems and sub-systems through the PCI port during system validation.
The HP E2975A PCI Protocol Permutator and Randomizer Software is a C-API library to set up deterministic protocol variations using a sophisticated permutation algorithm.
A standalone 4 slot PCI backplane featuring bus arbitration and clock distribution allows card manufacturers to set up and test environment for timing measurements and card evaluation.

(See the colored brochure, pub# 5965-4723E: HP E2920 Computer Verification Tools, PCI Series.)

[ Features ]
The HP E2925A a programmable PCI master and target with on-board PCI state analyzer, featuring:

Control of master and target protocol and traffic behavior for traffic emulation and debugging.

PCI state logic analyzer 32 k (1 M optional) with PCI-oriented triggering and storage qualification for convenient traffic analysis.

PCI protocol checker monitors 25 protocol rules in real-time for capturing violations (according to PCI Specification Rev 2.1).

Add-on comprehensive GUIs for convenient, interactive debugging performance analysis.

Control over RS232, PCI, or bi-directional Centronics.

Add-on, ready-to-run stress tests and protocol permutation library to intensify tests.

Optional trigger sequencer with 64 branches to trigger, store data, decrement and pre-load counter.

On-board 128 kB PCI memory and/or/ I/O space for emulating master and target resources.

Programmable configuration space/expansion EEPROM.

On-board CPU with built-in test functions for system data integrity testing.

C-API programming library for complete integration into your test environment.

CPU port and static I/O signals to read and write DUT registers and signals beyond PCI.

[ Specifications ]

The HP E2925A Specifications are in accordance to the PCI Specification, Rev. 2.1. For detailed specification info refer to the Technical Data Sheet! see: Key Literature , HP E2925A Technical Data Sheet pub# 5965-4724E. Key Specifications: ------------------- Signal definition

All 32 bit PCI bus signals (except JTAG) and internal state information can be observed by the logic analyzer and used by the pattern recognizer to trigger the analyzer or exerciser.

Bus commands, master

All command types, including "reserved", can be generated, except for dual address purposes.

Reserved commands 0100 and 1000 are treated as read commands.

Reserved commands 0101 and 1001 are treated as write commands.

It is up to the user to ensure that when using cache-line related commands, the number of data transfers correlates to the cache-line size.

Data is written from the on-board memory for write commands and read into the on-board memory for read commands.

Bus commands, target

Provides a configuration space and two decoders for the on-board memory, which can all be individually enable or disabled.

Decoder 1 responds to all types of memory cycles, if enabled.

Decoder 2 can be configured to respond to either I/O cycles or all memory cycles.

Configuration space responds to type 0 configuration cycles if enabled.

Target does not respond to interrupt acknowledge, special cycle, reserved commands or dual address cycles.

Addressing, master

Supports 32 bit addressing, and always generates a linear address order within a burst, independent of AD[1:0] sate.

Arbitration

Master: REQ# is asserted as soon as the first address and data of the programmed transfer have been prepared. By default, REQ# remains asserted until the transfer has been completed, even if it consists of multiple transactions.
This can be overridden by programming REQ# to be de-asserted during any address phase.

Component specification

PCI drivers are driven by Vio on the PCI connector and can be used in both 5 V and 3.3 V environments.

AD[31:0], C/BE[3:0], PAR, and PERR are driven by PCI-compliant buffers of Altera Flex81500A2-304ARC FPGA.

FRAME#, IRDY#, REQ#, DEVSEL#, STOP#, and TRDY# are driven by PCI-compliant buffers of Altera Flex81188A2-208AQP FPGA.

Clock specification

Operates at any frequency between DC and 33 MHz.

Timing parameters

Symbol | Min | Max ---------------------------- tval | | 12 ns ton | 2 ns | toff | | 28 ns tsu | 7 ns | tsu (ptp) | 7 ns | th | 0 ns | @ temperature of -40 °C to +70 °C

Configuration space

The HP E2925A has a complete, fully programmable, single function configuration access. Bits and values which are normally fixed in a standard PCI device can be programmed.

Device identification

Vendor ID, device ID, revision ID, header type, and class code are programmable.

Expansion ROM

64 kB EEPROM is available as expansion ROM and is mapped (repeated four times) into a 256 kB address space, starting at the address assigned in the expansion ROM BAR.

The EEPROM is fully programmable and retains its contents if power is cycled.

Operating temperature

-40°C to +70°C

[ Ordering ]

HP E2925A 32 bit, 33 MHz PCI Analyzer and Exerciser consists of: - 32 bit, 33 MHz PCI Exerciser and Analyzer card - C application programming interface library for MS-DOS^®, Windows 3.1, Windows 95, and Windows NT - Command line interface software for Windows 95/NT - Software ID module to enable add-on software products Opt 001 External Power Supply For applications where the exerciser and Analyzer card should be transparent to the system, you can connect this external power supply to prevent the card form drawing power from the slot. Opt 002 Fast Host Interface For applications requiring extensive data download/upload from an external test controller to the system under test you can improve the data throughput through the Exerciser and Analyzer card by using the Bi-directional Centronics interface instead of the RS232 interface. This option includes an ISA Bi-directional Centronics interface card for your controlling PC and the appropriate cable to connect it to the HP E2925A. Opt 003 HP Logic Analyzer Adapter This add-on daughter card provides all of the on-board PCI analyzer signals with the appropriate terminations and connectors to connect straight to an external HP Logic Analyzer. This is useful if you want to observe the PCI bus state in contact with other busses or interfaces in the system under test. Opt 004 General Logic Analyzer Adapter Plug-on adapter card providing unterminated connectors for connecting any logic analyzer. Opt 100 1M trace memory / performance board This add-on daughter card expands the HP E2925A by 1M trace memory, real-time counter and trigger sequencer.

To use the HP E2925A as an interactive PCI Analyzer and Exerciser you should use the add-on Graphical User Interface products which are available as part of the HP E2920 Computer Verification Tools, PCI series. These GUIs let you set-up and use the PCI Analyzer or PCI Exerciser for different applications without needing to program the card or understand the C-API. HP E2970A PCI Analyzer graphical user interface for Windows 95/NT HP E2971A PCI Exerciser graphical user interface for Windows 95/NT HP E2972A PCI Performance Analyzer software for Windows 95/NT HP E2974A PC Subsystem Stress Test software for Windows 95/NT HP E2975A PCI Protocol Permutator and Randomizer software Interactive CD-Guide to optimizing PCI Performance for FREE This informative multimedia CD for the HP E2925A provides a comprehensive guide to optimizing PCI performance. In a question-and-answer format, the CD explains how you can achieve exact results using reliable methods and fast designs. A walk-through example shows technical basics as taught by leading PCI experts, and customers comments are presented in a video interview. Please ask your local HP representative for publication number: 5965-5882E.

Trademarks:
MS-DOS and Windows are U.S. registered trademarks of Microsoft Corporation. All other products and company names are trademarks/reg. trademarks of their respective holders.

[ Key Literature ]

HP E2925A Technical Data Sheet
HP E2970A Technical Data Sheet
HP E2971A Technical Data Sheet
HP E2972A Technical Data Sheet
HP E2974A Technical Data Sheet
HP E2975A Technical Data Sheet

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[ Related ]

Related Information:

HP E2910A PCI Bus Exerciser

Efficient Use of PCI (INTEL site)

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