HP E4201A 2.048 Mb/s (E1) Line Interface

The HP E4201A 2.048 Mb/s (E1) Line Interface generates and analyses ATM cell streams contained within a E1 framing format. It is a single-slot module that provides test capability at the physical and ATM cell layers for the HP E4200/E4210 Broadband Series Test System.

Line interface modules not only connect the device or system under test to your Broadband Series Test System, but also provide physical, convergence, and ATM cell testing capabilities. Transmission test functionality includes: traffic generation, cell error, loss and delay measurements, and traffic capture and playback.

The E4201A 2.048 Mb/s (E1) Line Interface can be used in conjuction with other BSTS line interfaces, dedicated test modules, and test software to perform these tests.

The HP E4200/E4210 Broadband Series Test System (BSTS) is ideal for R&D engineering, product development, field trials and quality assurance. The industry-standard R&D performance and conformance tester that offers the most transmission and protocol technologies on a single platform, the BSTS is ideal for Frame Relay/ATM interworking testing. You can test both sides of an interworking function or device with a single BSTS since timestamps and statistics are synchronized between all modules in a BSTS chassis, allowing correlation of events and times between physical ports.

Line interface modules can perform physical layer testing with a minimal BSTS configuration consisting of a line interface module and chassis.

Complete range of test software applications and dedicated test modules is available to perform upper layer testing.

Add the HP E4209 Cell Protocol Processor provides monitoring and simulation test functions at the ATM and adaptation layer by executing optional protocol testing software applications. The CPP performs many functions in hardware that are usually done in software -- such as an automatic segmentation and reassembly engine for sophisticated real-time ATM, AAL and other higher layer protocol testing.

The HP E4219A ATM Network Impairment Emulator module lets you find the limits of performance by inserting impairments into an ATM cell stream.

For complete list of BSTS Product Numbers, please refer to the Product Index page.

[ Features ]

Cell based implementation
Operates in Terminal, Monitor, Near-end Loopback, Far-end Loopback and Drop-and-Insert modes
Provides physical layer measurements as well as error and alarm generation
Internal traffic generator has 1 foreground channel and up to 100 background channels

[ Specifications ]

Modes
When using the coaxial front panel connectors, three modes are
available.

Terminal
Used when connecting the BSTS as an end device to the system under
test; complete traffic generation and analysis capabilities as
available.
                                 
Both the transmitted and received signals are active on to the same
connector (either TE or NT).

Monitor
Used when the BSTS is desired to be a passive tap; the received
signal from one connector is re-transmitted on other connector.
                                 
Signals moving in either direction can be monitored.

Near-End Loopback
Used to provide a local loopback to the BSTS; the BSTS's transmitter 
signal is electrically looped back to the BSTS's receiver.
                                 
The transmitter signal can be routed to either TE or NT connector.

Far-End Loopback
Used to provide a remote loopback to the system under test; the BSTS's 
received signal is electrically looped back to the system under test.
                                 
The received signal can be monitored by the receiver.

Drop and Insert
The BSTS's transmitter generates a signal on one connector, while the
BSTS's receiver analyses the signal received on the other connector.
                                 
The received signal from the active transmitter connector is
re-transmitted on the other connector.


ATM Cell Generation
The transmitted cell stream can contain ATM cells generated
internally by the E4201A, and ATM cells generated by an optional
E4209 Cell Protocol Processor module. ATM cells generated on-board
can consist of one foreground channel to stimulate the channel
under test, and up to one hundred background channels for loading
purposes. Fill cells are used to occupy unused bandwidth.

Total Bandwidth
1.920 Mb/s

Modes
User-Network Interface (UNI) or Network-Node Interface (NNI)

HEC
Automatic generation

Fill Cells
Idle or unassigned

Channel Priority Order
Foreground, background, CPP (highest to lowest priority)

Channel Control
VCI
VPI
GFC
Payload Type
Cell Loss Priority

SAR-PDU Support
AAL-0
AAL-1


Foreground Channel

Bandwidth
100 b/s to 1.920 Mb/s

Accuracy
±0.02 ppm

Distribution
Off
Single burst
Periodic (according to the specified bandwidth)

Channel Depth
1500 cells (variable)

Cell Payload
Timestamp
Single cell PRBS
Cross cell PRBS
Data pattern
Byte access


Background Channels

Number of Channels
Up to 100

Bandwidth
3 kb/s to 1.920 Mb/s

Accuracy
±10 ppm

Distribution
Off
Periodic

Channel Density
Bandwidth and cell distribution for each background channel is
individually assignable up to maximum bandwidth

Channel Depth
16 cells

Cell Payload
Single cell PRBS
Data pattern
Byte access


Cell Payloads

Payloads
Timestamp (32-bit departure timestamp value with 100 nanosecond 
resolution)
Cross cell PRBS-9
PRBS-15 (inverted and not inverted)
PRBS-23
Single cell PRBS-9
Data pattern or byte access

Data Patterns
User byte
AA55h or FF00h
Incrementing (value of each successive byte is incremented by 1)

Byte Access
Payload of all cells in the selected channel can be edited by the user 
in an active channel environment, or off-line as a sequence of PDUs

AAL-1 automatically inserts first payload byte containing SN/SNP
values and CSI bit


Erroring Control
Error conditions can be introduced to simulate alarm signals and
signal stressing. Error stressing is used to generate incorrect bytes 
in a test signal.

Error Stressing Control
Off
On
Pulse On (error condition is normally off; pulses on)
Pulse off (normally on; pulses off)
Sequence On (normally off; alternates on/off/on)
Sequence Off (normally on; alternates off/on/off)

ATM Error Injection              
Cell header or payload bytes with bit error masking

Cell Loss
Sequence Number in the SAR-PDU is skipped and a fill cell is inserted

PRBS Error Add
Single bit error add to the PRBS pattern in the cell payload


E1 Stressing

Alarm Generation
AIS
RAI

Error Injection
Bit errors (1e-3 to 1e-9 rate)


ATM & E1 Measurements
Measurements are sampled every 100 milliseconds and accumulated
over the user-specified measurement period. Results from the most
recent complete measurement period are retained.

Measurement Period
Ranges from 1 second to 3 days in resolutions of 1 second

Result Types
Cumulative or latched (based on most recent measurement period)

Result Formats
Count
Ratio
Seconds

ATM Cell Measurements
HEC errors
Corrected headers
Cell count
Cell bandwidth
Select Cell Not Received (SCNR) a seconds

Cell Delay Measurements
Cell delay
Inter-arrival time
Cell delay variation

Virtual Channel Errors
AAL-1 SN/SNP errors
Cell loss
PRBS errors
PRBS sync loss alarm seconds

E1 Measurements
Coding errors
CRC-4 errors
FEBE errors
Framing errors
Loss of signal alarm seconds
Out-of-frame alarm seconds
AIS alarm seconds
RAI alarm seconds
E1 multiframe count


Traffic Capture & Playback
Provides capture of 1500 cells from the selected ATM cell stream.
Capture is manual or event triggered. Manual triggering captures
1500 cells after the trigger. Event triggering captures 749 cells
pre-trigger, 1 trigger cell, and 750 cells post-trigger.

Manual
Triggered on user request

ATM Cell Triggers
Cell loss
Header error
PRBS error
SN/SNP byte error


Front Panel Connectors & Indicators

E1 Symmetrical Input and Output (TE)       
RJ45 connector
120 ohm impedance symmetrical 
2.048 Mb/s
0 dB (low level) or 20 dB (high level) for input
-4 dB (low level) or 0 dB (high level) for output
Internal (stratum 3), External, and Recovered clock modes

E1 Symmetrical Input and Output (NT)        
RJ45 connector
120 ohm impedance symmetrical
2.048 Mb/s
0 dB (low level) or 20 dB(high level) for input
-4 dB (low level) or 0 dB (high level)for output
Internal (stratum3), External, and Recovered clock modes

E1 Coaxial Input                
BNC connector
75 ohm impedance
2.048 Mb/s
0 dB (low level) or 20 dB (high level)

E1 Coaxial Output
BNC connector
75 ohm impedance
2.048 Mb/s
-4 dB (low level) or 0 dB (high level)
Internal (stratum 3), External, and Recovered clock modes

External Clock Input
SMB connector
TTL input
Nominal 50 ohm impedance

Tx and Rx Trigger Outputs      
SMB connectors
TTL output
Nominal 50 ohm impedance

LED Indicators
Failed
Error
Access
Gating
Signal
OOF
AIS
BIP
Yellow
SCNR
Reference Clock

[ Ordering ]

HP E4201A 2.048 Mb/s (E1) Line Interface

Requirements: Base system requirement: HP E4200A/B HP Broadband Series Test System Form 7 Transportable Base or HP E4210A/B HP Broadband Series Test System Form 13 Mainframe Base HP E4209A/B Cell Protocol Processor HP E4219A ATM Network Impairment Emulator

All orders include the following:
User's Guide Programmer's Guide Product Release Notice

[ Key Literature ]