HP E4205A 155 Mb/s (UTP-5) Line Interface

The HP E4205A 155 Mb/s Electrical UTP-5 Line Interface generates and analyses ATM cell streams contained within a SONET or SDH framing format. It is a single-slot VXI module that provides test capability at the physical and ATM cell layers for the HP E4200/E4210 Broadband Series Test System.

The HP E4205A is capable of operating in both a cell mode and in a SONET/SDH frame mode. This allows the user to not only examine ATM cells mapped into a SONET/SDH frame but also all of the SONET/SDH frame data.

Line interface modules not only connect the device or system under test to your Broadband Series Test System, but also provide physical, convergence, and ATM cell testing capabilities.

The industry-standard HP E4200/E4210 Broadband Series Test System (BSTS) is ideal for R&D engineering, product development, field trials and quality assurance. It supports the widest variety of standard interfaces of speeds up to 622 Mb/s, the broadest, most powerful range of signalling capabilities, the industry's most complete automated conformance test suites, time-savings features for monitoring, emulation, simulation, load generation, performance and automated testing.

Line interface modules can perform physical layer testing with a minimal BSTS configuration consisting of a line interface module and chassis.

Complete range of test software applications and dedicated test modules is available to perform upper layer testing.

Add the HP E4209 Cell Protocol Processor (CPP) provides monitoring and simulation test functions at the ATM and adaptation layer by executing optional protocol testing software applications. The CPP performs many functions in hardware that are usually done in software -- such as an automatic segmentation and reassembly engine for sophisticated real-time ATM, AAL and other higher layer protocol testing.

The HP E4219A ATM Network Impairment Emulator module lets you find the limits ofperformance by inserting impairments into an ATM cell stream.

For complete list of BSTS Product Numbers, please refer to the Product Index page.

[ Features ]

Cell based implementation
Operates in both cell and SONET/SDH frame modes
User-Network Interface (UNI) or Network-Node Interface (NNI) selections
Provides physical layer measurements as well as error generation
Internal traffic generator has 1 foreground channel and up to 100 background channels
Works with Cell Protocol Processor

[ Specifications ]

Modes
Three Tx/Rx modes are available. In Terminal mode, full signal 
generation and analysis functions are available. In Repeater mode, 
the received signal is re-transmitted (physical layer loopback). In 
Local Loopback mode, the transmit signal is electrically looped to 
the receiver.


ATM Cell Generation
The transmitted cell stream can contain ATM cells generated internally 
by the E4205A, and ATM cells generated by an optional E4209 Cell 
Protocol Processor (CPP) module. ATM cells generated on-board can 
consist of one foreground channel to stimulate the channel under test, 
and up to one hundred background channels for loading purposes. Fill 
cells are used to occupy unused bandwidth.

Total Bandwidth
48.384 Mb/s

Modes
User-Network Interface (UNI) or Network-Node Interface (NNI)

HEC
Automatic generation

Fill Cells
Idle or unassigned

Channel Priority Order
Foreground, background, CPP (highest to lowest priority)

Channel Control
VCI
VPI
GFC
Payload Type
Cell Loss Priority

SAR-PDU Support
AAL-0
AAL-1


Foreground Channel

Bandwidth
From 100 b/s to 149.76 Mb/s with a resolution of ±300 b/s

Accuracy
±3 b/s of selected value

Distribution
Off
Single burst
Periodic (according to the specified bandwidth)

Channel Depth
1500 cells (variable)

Cell Payload
Timestamp
Single cell PRBS
Cross cell PRBS
Data pattern
Byte access


Background Channels

Number of Channels
Up to 100

Bandwidth
3000 b/s to 149.76 Mb/s with a resolution of ±1.25 kb/s

Distribution
Off
Periodic

Channel Density
Bandwidth and cell distribution for each background channel is 
individually assignable up to maximum bandwidth

Channel Depth
16 cells

Cell Payload
Single cell PRBS
Data pattern
Byte access


Cell Payloads

Payloads
Time stamp (32-bit departure time stamp value with 100 nanosecond
resolution)
Cross cell PRBS-9
PRBS-15 (inverted and not inverted)
PRBS-23
Single cell PRBS-9
Data pattern or byte access

Data Patterns
User byte
AA55h or FF00h
Incrementing (value of each successive byte is incremented by 1)

Byte Access
Payload of all cells in the selected channel can be edited by the 
user in an active channel environment, or off-line as a sequence of 
PDUs

AAL-1 automatically inserts first payload byte containing SN/SNP 
values and CSI bit


Erroring Control
Error conditions can be introduced to simulate alarm signals and
signal stressing. Error stressing is used to generate incorrect bytes 
in a test signal.

Error Stressing Control
Off
On
Pulse On (error condition is normally off; pulses on)
Pulse Off (normally on; pulses off)
Sequence On (normally off; alternates on/off/on)
Sequence Off (normally on; alternates off/on/off)

ATM Error Injection
Cell header or payload bytes with bit error masking

Cell Loss
Sequence Number in the SAR-PDU is skipped and a fill cell is inserted

PRBS Error Add
Single bit error add to the PRBS pattern in the cell payload


SONET/SDH Features

SONET/SDH Stressing
SPE pointer errors can be introduced once or at a user defined 
sequence

Data errors can be introduced singly or at a rate of 1.0E-9 to 1.0E-3 
on to the Section BIP-8, Line BIP-24, Path FEBE and path BIP-8
          
Loss of signal for either a single frame, or continuous

Framing Formats
SONET STS-3c, SDH STM-1

TOH/SOH
Can be any user specified value between 00 and 0ffh (except B1 and B2 
bytes)

B1 and B2
Automatically calculated

D1 to D12
User specified

H1 to H3
SPE/AU4 pointer bytes may be set to any fixed value with or without 
NDF

Pointer Movement
Increment, decrement, or ramping

SPE/AU4 POH                      
Path overhead can be user specified except for B3 byte which is 
automatically calculated

J1
User specified 64 or 15 byte path trace message

G
Set Enhanced RDI-P to any of 8 values; REI-P can be user specified


ATM, SONET/SDH Measurements
Measurements are sampled every 100 milliseconds and accumulated
over the user-specified measurement period. Results from the most
recent complete measurement period are retained.

Measurement Period
Range 1 second to 3 days in resolutions of 1 second

Result Types
Cumulative or latched (based on most recent measurement period)

Result Formats
Count
Ratio
Seconds

ATM Cell Measurements
HEC errors
Corrected headers
Cell count
Cell bandwidth
Select Cell Not Received (SCNR) alarm seconds

Cell Delay Measurements
Cell delay
Inter-arrival time
Cell delay variation

Virtual Channel Errors
AAL-1 SN/SNP errors
Cell loss
PRBS errors
PRBS sync loss alarm seconds

SONET/SDH Measurements
Out of frame errors
Loss of frame alignment errors
Loss of pointer errors
Loss of cell synchronization errors
Loss of signal errors
Line AIS
Line FERF
Path AIS
Path FERF
Path yellow
Section BIP
Line BIP
Path BIP
Path FEBE
Line FEBE
Uncorrected HEC error


ATM Capture
Provides capture of 1500 cells from the selected ATM cell stream.
Capture is manual or event triggered. Manual triggering captures
1500 cells after the trigger. Event triggering captures 750 cells
pre-trigger, and 750 cells post-trigger.

Manual
Triggered on user request

ATM Cell Triggers
Cell loss
Header error
PRBS error
SN/SNP byte error


SONET/SDH Capture
When in SONET/SDH frame mode, the E4205 line interface captures and
displays TOH data, POH data and path trace messages.


Front Panel Connectors And Indicators

To NE
To Network-Equipment connector
RJ-45 Connector
1.0 V into 100 ohms
100 ohm balanced impedance

To UE
To User Equipment connector
RJ-45 Connector
1.0 V into 100 ohms
100 ohm balanced impedance

Reference Clock Input
BNC connector
10 dbm into 50 ohms
155.52 MHz with better than a
60/40% duty cycle

Rx and Tx Trigger Outputs
BNC connectors
TTL outputs

LED Indicators
Failed
Error
Access
Ref Clk
Gating
Signal
AIS
BIP
SCNR
FERF
LOCS
OOF

[ Ordering ]

HP E4205A 155 Mb/s Electrical UTP-5 Line Interface

Requirements: Base system requirement: HP E4200A/B HP Broadband Series Test System Form 7 Transportable Base or HP E4210A/B HP Broadband Series Test System Form 13 Mainframe Base HP E4209A/B Cell Protocol Processor HP E4219A ATM Network Impairment Emulator

All orders include the following:
User's Guide Programmer's Guide Product Release Notice

[ Key Literature ]