HP E4206A T1/E1 Frame Processor Module

The HP E4206A T1/E1 Frame Processor is a high-performance hardware module that tests frame-based protocols at speeds up to 2 Mb/s. Two integrated T1/E1 interfaces and internal RISC-based protocol test engines can each monitor, capture traffic, and generate statistics -- even with heavily loaded links and short frame lengths. The HP E4206A can also generate alarms and framing errors, and provide sophisticated traffic generation functionality when used with optional test software applications.

The two physical ports and internal protocol test engines can be combined in different configurations to achieve several different test configurations. Each protocol test engine works with one channel of user-selectable timeslots. In dual-port mode, each physical port is connected to a protocol test engine for independent testing. In pass-through mode, one channel from one port is tested while other timeslots are passed through to the other port. In dual-channel-mode, two separate channels from one physical port can be tested; the second physical port is not used in this configuration.

A companion product, the HP E4207A V Interface Frame Processor, is functionally similar to the HP E4206A but has integrated interfaces which support V.11, V.28, V.35, V.36 and EIA 530 physical connections.

When used with the HP E4216A Frame Relay Test Software, the HP E4206A can decode and display frames, as well as generate traffic (with encoding and decoding of DL-CORE frames).

The decoded English-language display uses the same terminology found in standards documents. Errors are automatically detected and highlighted on-screen, complete with explanatory messages. Traffic can be displayed with a live viewer, captured in memory, or logged to disk. Capture up to 4 MB of traffic per port, or loop indefinitely and stop when a specified event occurs. For example, capture all traffic sent to a specified data link control identification and stop when a framing error occurs. Captured information can be analyzed off-line with a playback viewer.

The HP E4216A executes on an HP E4206A T1/E1 Frame Processor in addition to an HP E4209B Cell Protocol Processor. Traffic generation, triggering, filtering and statistics capabilities described in this datasheet are provided by an HP E4206A/E4216A combination.

The HP E4216A Frame Relay Test Software package also includes LMI monitoring and emulation functions.

The industry standard HP E4200/E4210 Broadband Series Test System (BSTS)is ideal for R&D engineering, product development, field trials and quality assurance. It offers the most transmission and protocol technologies on a single platform. The BSTS is ideal for Frame Relay/ ATM interworking testing. The BSTS also has LAN testing capabilities, making it ideal for testing LAN interworking via Frame Relay backbones.

You can test both sides of an interworking function or device with a single BSTS. In addition, timestamps and statistics are synchronized between all modules in a BSTS chassis, allowing correlation of events and times between physical ports.

[ Features ]

Dual ports (2 Interfaces, 2 Application Processors)
Frame-based operation with 20 plus real-time measurements
Switchable between T1 and E1
Channelized/Unchannelized/Fractional Operation
Bit mask provides for flexible bit stream selection (56/64 Kb/s, nx 56/64 Kb/s etc)
2 timeslots (actually bit streams) can be routed to 2 Application Processors)
Sophisticated high performance traffic generation capability

[ Specifications ]

Real-Time Dual-Port Monitoring

Multiport Monitoring             
Dual-port mode
Dual-channel/single-port mode
Pass-through mode
Synchronized timestamps correlates events from two physical ports
Protocol viewer works with live traffic or plays back captured data
4 MB capture buffer per port

Modes                            
Passive monitor
Network termination (emulate network)
Terminal equipment (emulate user)

Clock Sources                    
Loop (line)
Local
External clock reference

Decode Displays                  
Summary mode; displays a single line description of each PDU

Detailed mode; displays a multi-line description of each event with 
field-by-field decoding; includes header/trailer and payload options
                                 
Hex mode; displays the entire PDU in hexadecimal format
                                 
Timestamps; toggle on/off the display of timestamps
   
Port identifier; toggle on/off the display of the VXI slot number of
the Frame Processor from which the data was captured; also indicates
whether the captured data was transmitted or received

Summary Display Contents         
Event header
Most significant error in PDU (if any)
DL-CORE information, including
DLCI (data link connection identifier), FECN (forward explicit congestion 
notification), BECN (backward explicit congestion notification), and 
discard eligibility (DE) bits

Detailed Display Contents        
Field-by-field decode of each header and trailer field
                              
Decode Errors                    
Aborted frames
Frame does not have an integral number of octets
Frame is too large
Frame is too small
Address size is too large
Address size is too small
Less than 3 octets between address and end flag
Invalid frame check sequence (FCS) or cyclical redundancy check (CRC-16)

T1 Alarm Detection      
Loss of signal (LSL)
Loss ofsynchronization (LOS)
Remote alarm indication (RAI)
Alarm indication signal (AIS)

E1 Alarm Detection               
Loss of signal (LSL)
Loss of synchronization (LOS)
Signalling all zeroes (SA0)
Signalling all ones (SA1)
Unframed all ones (UA1)
Remote alarm indication (RAI)
Distant multiframe alarm (DMF)

BOP Filters                      
Frame check sequence (FCS) errors
Aborted frames
Non-octet aligned frames
Block frames
Layer 1 events
Trace statements

BOP Triggers                     
Frame check sequence (FCS) errors
Aborted frames
Non-octet aligned frames
Capture buffer full
Time of day
External trigger input

Pattern Matching                
Passes or blocks frames which match a 64-byte user-defined pattern

T1/E1 Triggers                   
Loss of signal level (LSL)
Loss of synchronization (LOS)
Remote alarm indication (RAI)
Alarm indicationsignal (AIS)
Distant multiframe alarm (DMF)

Frame Relay Filters & Triggers
Up to four data link connection identifiers (DLCIs) can be specified
Forward explicit congestion notification (FECN) bit
Backward explicit congestion notification (BECN) bit
Discard eligibility (DE) bit                                 
Address length of 2, 3 or 4 octets
Short frame
Long frame
Invalid header

Trigger Actions                 
Start/stop collecting statistics
Start/stop capture
Generate a trace statement
Display a message
Notify user program
Pulse external trigger output

Trigger Controls                 
Delayed trigger activation
Specify delay in frames of 0 to 100 milliseconds

Display Filter Controls          
Filter on selectable layer
Filter on all events, matched events, or no events
Filter on address field/s, DLCI size, D/C=0 or D/C=1
Filter on any of the above decode errors


High-Performance Traffic Generation

Traffic Streams & Controls       
Generate up toeight simultaneous streams
Selectable throughput in kb/s and percent load parameters for each stream
Constant, burst or random traffic distributions with distribution
parameters individually selectable for each stream

Traffic Options(Stream 1 only)                  
Embed 48-bit timestamps
Embed 32-bit sequence numbers
Truncate frame length to specified number of octets
Increment frame length over a specified range
Randomly select frame length from within a specified range

Error Insertion                  
Send aborted frames
Send non-octet aligned frames
Invalid frame check sequence (FCS)

Alarm Generation                 
Remote alarm indication (RAI)
Alarm indication signal (AIS)
Distant multiframe alarm (DMF)


Real-Time Measurements

T1 D4 12 MF Framing Errors       
Bipolar
Ft bit
Fs bit

T1 D4 4MF Framing Errors         
Bipolar
Ft bit

T1 ESF Framing Errors      
Bipolar
Cyclical redundancy check(CRC)
Frame pattern sequence framing error(FPS)

E1 PCM30 CAS Framing Errors      
Bipolar
Frame alignment signal (FAS)

E1 PCM30 CCS Framing Errors      
Bipolar
Frame alignmentsignal (FAS)

E1 CRC4 CAS Framing Errors       
Bipolar
Cyclical redundancy check (CRC)
Frame alignment signal (FAS)
Multiframe alignment signal (MFAS)

E1 CRC4 CCS Framing Errors       
Bipolar
Cyclical redundancy check (CRC)
Frame alignment signal (FAS)
Multiframe alignment signal (MFAS)

BOP Measurements                 
Bits per second
Number of frames
Frames per second
Minimum, average and maximum frame length
Number of aborted frames
Number of non-octet-aligned frames
Number of frames matching a user-defined 64-byte pattern
Number of frame check sequence (FCS) errors


User Programming

Sample Programs                  
T1/E1 port setup
Delay measurement
LMI emulation
Lost frame,delay measurements, and payload integrity check for
Frame Relay/ATM interworking


Applicable Standards
         
ANSI T1.403 Network-to-Customer Installation DS1 Metallic Interface

Bellcore TR-NWT-000170 Digital Cross-Connect System Requirements and 
Objectives, January 1993

AT&T Publication 62411

ITU Recommendation G.703 (04/91) - Physical/electrical characteristics 
of hierarchical digital interfaces

ITU Recommendation G.704 (07/95) - Synchronous frame structures used
at 1544, 6312, 2048, 8488 and 44  726 Kbit/s hierarchical levels

ITU Recommendation G.742 (1988) -  Second order digitalmultiplexing
equipment operating at 8448 kbit/s and using positive justification

ITU Recommendation G.823 (03/93) - The control of jitter and wander
within digital networks which are based on the 2048 kbit/s hierarchy

[ Ordering ]

HP E4206A T1/E1 Frame Processor Module

Requirements: Base system requirement: HP E4200A/B HP Broadband Series Test System Form 7 Transportable Base or HP E4210A/B HP Broadband Series Test System Form 13 Mainframe Base To test native Frame Relay, select a frame processor and add a Frame Relay test software package: HP E4216A Frame Relay Test Software HP E4207A V Interface Frame Processor To test Frame Relay over AAL-5, the following modules are required: HP E4216A Frame Relay Test Software HP E4212A AAL Test Software HP E4209A/B Cell Protocol Processor HP E4118A T1-E1 Adapter Cables Opt 008 RJ-48 Y-Adaptor Cable Opt 010 Bantam Y-Adaptor Cable Opt 015 DB-15 Y-Adaptor Cable Opt 101 DB-9 Y-Adaptor Cable Opt 102 BNC Y-Adaptor Cable Opt 104 RJ-48 Adaptor Cable (Japanese pinout, female RJ-48 connector only) Unless noted otherwise, these cables are in a Y configuration with a male RJ-48 connector at one end, and both male and female versions of the adapted connector at the other end.

All orders include the following:
The HP E4206A includes two integrated T1/E1 physical interfaces, so line interface modules are not required. The front panel has RJ-48 and mini-bantam connectors. It also includes a User's Guide, Programmer's Guide and Product Release Notice.

[ Key Literature ]

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[ Related ]

Related product families available online:

Broadband Series Test System

Broadband/ATM