HP E4829B Parallel Cell/Traffic Generator and Analyzer System

The HP E4829B parallel cell/traffic generator and analyzer system is a comprehensive verification and debugging tool for today's cell based communication designs like ATM chips, ASICs, hubs, switches, and cross-connects. Connecting to parallel interfaces like the 8/16 bit wide UTOPIA level 1 and 2 or similar proprietary interfaces, the system meets the requirements for design verification of chips, ASICs and sub modules, as well as speeding up board/system debugging and root cause analysis. The concept of building cells out of single real-time generated and memory-based data segments allows you to handle standard ATM cells as well as proprietary ones, e.g., ATM cells with additional routing tags. Four independent traffic generators support single, periodic, and random cell burst. Full deterministic cell traffic can be set up. The cell trigger capabilities allow the user to detect dedicated cells, cell patterns, CRC-10, and HEC errors at real time as an event. Single or multiple events can be combined to start cell acquisition, event count or real-time processing like time stamp analysis for statistical measurements.

[ Features ]

Flexible cell structure and size from 16 to 128 word cell length
Exercise ATM switch fabric by stimulating and analyzing cells with routing tag added to the standard ATM cell structure
Flexible traffic shaping
Verify policing functions of ATM fabric
Stress physical devices for proper operation at corner cases
Real-time HEC, CRC-10, time stamping generation and analysis
Measures cell error ratio, cell transit delay, cell transit variation, cell loss, header translation
Connects to 8/16 bit custom or UTOPIA level 1 and 2 interfaces

[ Specifications ]

Connection Specifications

Connections:

8/16 bit data, parity, SOC, clock, handshakes (UTOPIA) or data valid/strobe (custom) and 8 additional auxiliary channels

Data clock: 90kHz to 52 MHz, internal or external

Cell Specifications

Cell length from 16 to 128 words, cell structure user constructable providing predefined segments (ATM UNI/NNi Header), algorithmic generated segments (HEC, CRC-10, PRBS) and memory based segments (routing tag, payload). The auxiliary channels provide memory based segments

Transmitter data memory Specifications

Traffic shaping Specifications

       Tcell:     distance between two consecutive cells
       Tpause:    distance between two bursts of cells
       Count:     number of cells within one cell burst

Analysis Specifications

Data acquisition with data memory depth of 128k
(captures up to 2400 cells @ 8 databit; up to 4800 cells @ 16 databit)

[ Ordering ]

Entry System HP E4829B Parallel Cell/Traffic Generator and Analyzer System consists of: 13 slot VXI frame, embedded series 700 controller, disk module, one HP E4821A Hardware module, and HP E4871A Graphical User Interface Opt 101 Qty. 2 HP E4889A active TTL RX/TX PODs and software license supporting UTOPIA level 1 and similar custom interfaces Opt 102 One HP E4885A active TTL TX and one HP E4886A RX POD and software license for UTOPIA level 2 interfaces As add-on to a Broadband Series Test System HP E4821A Hardware module Opt 101 see HP E4829B Opt 101 Opt 102 see HP E4829B Opt 102 HP E4871A Graphical User Interface For detailed pricing and specific system configurations please contact your local Hewlett-Packard sales office. Monitor, keyboard and mouse must be ordered separately!

All orders include the following:
(English Installation and Getting Started Guide E4829-91010)

[ Key Literature ]

HP E4829B Interface Cable Kits
Implementation of UTOPIA level 2 with HP E4829B
Real Time Bit Error Rate Analysis
Cell Transfer Time Measurement with HP E4829B
HP E4829B Product Overview
HP E4829B Configuration Guide
HP E4829B Technical Data Sheet

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[ Assistance ]

To help you make the right instrument choices

Local Sales Office

[ Related ]

Related product families available online:

Broadband/ATM