/*!
**********************************************************
* \brief
*    dma configuration registers address definition
* \author
*    generated by reg_table automatically,dont modify it
**********************************************************
*/
#ifndef __DMA_MAP_H
#define __DMA_MAP_H
#include "adt3102_type_define.h"
//#define dmair_dma_int_status 0x00

//#define dmair_dma_int_mask 0x01

//#define dmair_dma_int_clear 0x02

//#define dma_0_config 0x03
#define dma_0_config_0_en_bit ((uint32)1<<31)
#define dma_0_config_0_pause_bit (1<<30)
#define dma_0_config_0_src_inc_bit (1<<29)
#define dma_0_config_0_src_size_shift 27
#define dma_0_config_0_src_size_mask ((1<<2)-1)
#define dma_0_config_0_dst_inc_bit (1<<26)
#define dma_0_config_0_dst_size_shift 24
#define dma_0_config_0_dst_size_mask ((1<<2)-1)
#define dma_0_config_0_mem_to_mem_bit (1<<23)
#define dma_0_config_0_mem_to_peri_bit (1<<22)
#define dma_0_config_0_peri_sel_shift 18
#define dma_0_config_0_peri_sel_mask ((1<<4)-1)
#define dma_0_config_0_pri_bit (1<<17)
#define dma_0_config_0_circ_bit (1<<16)
#define dma_0_config_0_cfg_cnt_shift 0
#define dma_0_config_0_cfg_cnt_mask ((1<<16)-1)

//#define dma_0_src_addr 0x04

//#define dma_0_dst_addr 0x05

//#define dma_0_tcnt 0x06

//#define dma_1_config 0x07
#define dma_1_config_1_en_bit ((uint32)1<<31)
#define dma_1_config_1_pause_bit (1<<30)
#define dma_1_config_1_src_inc_bit (1<<29)
#define dma_1_config_1_src_size_shift 27
#define dma_1_config_1_src_size_mask ((1<<2)-1)
#define dma_1_config_1_dst_inc_bit (1<<26)
#define dma_1_config_1_dst_size_shift 24
#define dma_1_config_1_dst_size_mask ((1<<2)-1)
#define dma_1_config_1_mem_to_mem_bit (1<<23)
#define dma_1_config_1_mem_to_peri_bit (1<<22)
#define dma_1_config_1_peri_sel_shift 18
#define dma_1_config_1_peri_sel_mask ((1<<4)-1)
#define dma_1_config_1_pri_bit (1<<17)
#define dma_1_config_1_circ_bit (1<<16)
#define dma_1_config_1_cfg_cnt_shift 0
#define dma_1_config_1_cfg_cnt_mask ((1<<16)-1)

//#define dma_1_src_addr 0x08

//#define dma_1_dst_addr 0x09

//#define dma_1_tcnt 0x0a

//#define dma_2_config 0x0b
#define dma_2_config_2_en_bit ((uint32)1<<31)
#define dma_2_config_2_pause_bit (1<<30)
#define dma_2_config_2_src_inc_bit (1<<29)
#define dma_2_config_2_src_size_shift 27
#define dma_2_config_2_src_size_mask ((1<<2)-1)
#define dma_2_config_2_dst_inc_bit (1<<26)
#define dma_2_config_2_dst_size_shift 24
#define dma_2_config_2_dst_size_mask ((1<<2)-1)
#define dma_2_config_2_mem_to_mem_bit (1<<23)
#define dma_2_config_2_mem_to_peri_bit (1<<22)
#define dma_2_config_2_peri_sel_shift 18
#define dma_2_config_2_peri_sel_mask ((1<<4)-1)
#define dma_2_config_2_pri_bit (1<<17)
#define dma_2_config_2_circ_bit (1<<16)
#define dma_2_config_2_cfg_cnt_shift 0
#define dma_2_config_2_cfg_cnt_mask ((1<<16)-1)

//#define dma_2_src_addr 0x0c

//#define dma_2_dst_addr 0x0d

//#define dma_2_tcnt 0x0e

//#define dma_3_config 0x0f
#define dma_3_config_3_en_bit ((uint32)1<<31)
#define dma_3_config_3_pause_bit (1<<30)
#define dma_3_config_3_src_inc_bit (1<<29)
#define dma_3_config_3_src_size_shift 27
#define dma_3_config_3_src_size_mask ((1<<2)-1)
#define dma_3_config_3_dst_inc_bit (1<<26)
#define dma_3_config_3_dst_size_shift 24
#define dma_3_config_3_dst_size_mask ((1<<2)-1)
#define dma_3_config_3_mem_to_mem_bit (1<<23)
#define dma_3_config_3_mem_to_peri_bit (1<<22)
#define dma_3_config_3_peri_sel_shift 18
#define dma_3_config_3_peri_sel_mask ((1<<4)-1)
#define dma_3_config_3_pri_bit (1<<17)
#define dma_3_config_3_circ_bit (1<<16)
#define dma_3_config_3_cfg_cnt_shift 0
#define dma_3_config_3_cfg_cnt_mask ((1<<16)-1)

//#define dma_3_src_addr 0x10

//#define dma_3_dst_addr 0x11

//#define dma_3_tcnt 0x12

//#define dma_4_config 0x13
#define dma_4_config_4_en_bit ((uint32)1<<31)
#define dma_4_config_4_pause_bit (1<<30)
#define dma_4_config_4_src_inc_bit (1<<29)
#define dma_4_config_4_src_size_shift 27
#define dma_4_config_4_src_size_mask ((1<<2)-1)
#define dma_4_config_4_dst_inc_bit (1<<26)
#define dma_4_config_4_dst_size_shift 24
#define dma_4_config_4_dst_size_mask ((1<<2)-1)
#define dma_4_config_4_mem_to_mem_bit (1<<23)
#define dma_4_config_4_mem_to_peri_bit (1<<22)
#define dma_4_config_4_peri_sel_shift 18
#define dma_4_config_4_peri_sel_mask ((1<<4)-1)
#define dma_4_config_4_pri_bit (1<<17)
#define dma_4_config_4_circ_bit (1<<16)
#define dma_4_config_4_cfg_cnt_shift 0
#define dma_4_config_4_cfg_cnt_mask ((1<<16)-1)

//#define dma_4_src_addr 0x14

//#define dma_4_dst_addr 0x15

//#define dma_4_tcnt 0x16

//#define dma_int_sel 0x17

//#define dma_to_thld 0x18

//#define dma_clr_spi_req 0x19
#define dma_clr_spi_req_spi1_txdma_clr_sel_shift 9
#define dma_clr_spi_req_spi1_txdma_clr_sel_mask ((1<<3)-1)
#define dma_clr_spi_req_spi1_rxdma_clr_sel_shift 6
#define dma_clr_spi_req_spi1_rxdma_clr_sel_mask ((1<<3)-1)
#define dma_clr_spi_req_spi0_txdma_clr_sel_shift 3
#define dma_clr_spi_req_spi0_txdma_clr_sel_mask ((1<<3)-1)
#define dma_clr_spi_req_spi0_rxdma_clr_sel_shift 0
#define dma_clr_spi_req_spi0_rxdma_clr_sel_mask ((1<<3)-1)

//#define dma_0_addr_step 0x1a
#define dma_0_addr_step_0_dst_addr_step_shift 16
#define dma_0_addr_step_0_dst_addr_step_mask ((1<<16)-1)
#define dma_0_addr_step_0_src_addr_step_shift 0
#define dma_0_addr_step_0_src_addr_step_mask ((1<<16)-1)

//#define dma_1_addr_step 0x1b
#define dma_1_addr_step_1_dst_addr_step_shift 16
#define dma_1_addr_step_1_dst_addr_step_mask ((1<<16)-1)
#define dma_1_addr_step_1_src_addr_step_shift 0
#define dma_1_addr_step_1_src_addr_step_mask ((1<<16)-1)

//#define dma_2_addr_step 0x1c
#define dma_2_addr_step_2_dst_addr_step_shift 16
#define dma_2_addr_step_2_dst_addr_step_mask ((1<<16)-1)
#define dma_2_addr_step_2_src_addr_step_shift 0
#define dma_2_addr_step_2_src_addr_step_mask ((1<<16)-1)

//#define dma_3_addr_step 0x1d
#define dma_3_addr_step_3_dst_addr_step_shift 16
#define dma_3_addr_step_3_dst_addr_step_mask ((1<<16)-1)
#define dma_3_addr_step_3_src_addr_step_shift 0
#define dma_3_addr_step_3_src_addr_step_mask ((1<<16)-1)

//#define dma_4_addr_step 0x1e
#define dma_4_addr_step_4_dst_addr_step_shift 16
#define dma_4_addr_step_4_dst_addr_step_mask ((1<<16)-1)
#define dma_4_addr_step_4_src_addr_step_shift 0
#define dma_4_addr_step_4_src_addr_step_mask ((1<<16)-1)

// DMA 
typedef struct
{
  __IO uint32 dmair_dma_int_status ;
  __IO uint32 dmair_dma_int_mask ;
  __IO uint32 dmair_dma_int_clear ;
  __IO uint32 dma_0_config ;
  __IO uint32 dma_0_src_addr ;
  __IO uint32 dma_0_dst_addr ;
  __IO uint32 dma_0_tcnt ;
  __IO uint32 dma_1_config ;
  __IO uint32 dma_1_src_addr ;
  __IO uint32 dma_1_dst_addr ;
  __IO uint32 dma_1_tcnt ;
  __IO uint32 dma_2_config ;
  __IO uint32 dma_2_src_addr ;
  __IO uint32 dma_2_dst_addr ;
  __IO uint32 dma_2_tcnt ;
  __IO uint32 dma_3_config ;
  __IO uint32 dma_3_src_addr ;
  __IO uint32 dma_3_dst_addr ;
  __IO uint32 dma_3_tcnt ;
  __IO uint32 dma_4_config ;
  __IO uint32 dma_4_src_addr ;
  __IO uint32 dma_4_dst_addr ;
  __IO uint32 dma_4_tcnt ;
  __IO uint32 dma_int_sel ;
  __IO uint32 dma_to_thld ;
  __IO uint32 dma_clr_spi_req ;
  __IO uint32 dma_0_addr_step ;
  __IO uint32 dma_1_addr_step ;
  __IO uint32 dma_2_addr_step ;
  __IO uint32 dma_3_addr_step ;
  __IO uint32 dma_4_addr_step ;
}DMA_TypeDef;

#endif

