This is defined as the time that it takes for the PLL to change from one frequency to another for a given frequency step size to within a given tolerance. Refer to: "Switching (Lock time)" slide of the PLL Performance Presentation Phase noise will increase by 6 dB. The phase noise will increase by a factor of 10*log(N). Refer to: "Table of Transfer Functions" slide of the PLL Performance Presentation, and pg 36 of PLL Performance, Simulation and Design, by Dean Banerjee. 75% reduction. Refer to: "About the Fastlock Glitch" slide of the PLL Performance Presentation closed loop. Refer to: "Loop Bandwidth" slide of  of the PLL Performance Presentation LMX2324 Refer to: Single Integer PLLs in the parametric table