• Answers will vary, but will be around 5.5 KHz.
  Refer to: WEBENCH™ EasyPLL Online Simulation Tools, to do this, set the lock time constraint to 500 uS and design for minimum spur gain.
  
  
  
  
  
  
  
  
  
  
  
  
  
  
• sqrt(889*915)=901.9.
  Refer to: WEBENCH™ EasyPLL Online Simulation Tools, help file for N counter value.
  
  
  
  
  
  
  
  
  
  
  
  
  
  
• If you set the minimum and maximum output frequencies to be the same, it will say to design such that the VCO noise equals the PLL noise at the loop bandwidth.
  Refer to: WEBENCH™ EasyPLL Online Simulation Tools, help section for the loop bandwidth.
  
  
  
  
  
  
  
  
  
  
  
  
  
  
• Allows you to:
  • Specify your PLL system requirements    
  • Choose the best parts that meet your requirements.    
  • Determine your Loop Filter Components    
  • Analyze the simulation results    
  • Examine various wave forms    
  • Change parameters in any order    
  • Order a Custom Eval Board when you are done.

Refer to: Loop Filter Optimization presentation from Online Seminar (page 13)