Experimenting with a Stellex YIG Oscillator - Part 2

Overview

This is the second part of the Stellex YIG oscillator experiments which will be using the matching synthesizer board that is often sold along with the Stellex/Endwave miniYIGs.

The main components of the synthesizer board consist of a National LMX2326 PLL with a United Monolithic CND2050 "divide-by-4" prescaler feeding it, a couple of Sirenza SNA-176 MMIC gain stages, a MtronPTI K1526CMQA voltage-controlled oscillator for the PLL's 10 MHz reference, a National LMC6482 op-amp for the active PLL loop filter, and a couple of Motorola TCA0372 high-current op-amps to drive the tuning coils of the YIG.

There is a microstripline directional coupler which samples the RF output from the YIG, which then feeds the MMIC gain stages before entering the CND2050 prescaler.  The "divided-by-4" RF output from the prescaler is connected to the RF input pin of the LMX2326 PLL.  The synthesizer board requires a clean (external) source of +8.5 and +5 VDC.  The +8.5 VDC input will also power the YIG and its overall current draw will be around 500 mA.

The synthesizer board also requires an external means to program the National LMX2326 PLL.  John Miles (KE5FX) has an excellent little Windows program to control the LMX2326 PLL directly via a computer's parallel port.  This will be handy for the initial testing of this project.  Example PICBasic source code for a Microchip PIC16F84 will be given at the end of this article if you wish to further experiment programming the LMX2326 without the need for a computer.

There is a 20-pin main connector on the synthesizer board which allows access for the DC voltage inputs and the PLL's Clock, Data, and Load Enable lines.  There is also an optional "YIG On/Off" control, and a means to tweak the internal 10 MHz reference signal which can be used to slightly tune the final YIG RF output frequency.

The stock synthesizer boards work fine, but there are a few tricks and modifications you can do to improve their performance.  On the microstripline directional coupler input there is a 3 dB attenuator pad.  This can be removed if you wish to increase the final output RF power from the sampling directional coupler.  Another modification is using an external 10 MHz reference source.  The stock MtronPTI K1526CMQA isn't ideal, and using a higher quality reference source can reduce phase noise/jitter on the final YIG RF output signal.

The pinout and description for the 20-pin (gray) connector is:

Pin  Description      Pin   Description

1    Ground           11    YIG On/Off (Connect to +5 VDC through a 1 kohm resistor)
2    Ground           12    LMX2326 Load Enable
3    Ground           13    No Connect
4    Ground           14    LMX2326 Lock Detect (Low on PLL unlock)
5    +5 VDC Input     15    +8.5 VDC Input
6    +5 VDC Input     16    +8.5 VDC Input
7    LMX2326 Clock    17    Ground
8    No Connect       18    Ground
9    No Connect       19    10 MHz Reference Output
10   LMX2326 Data     20    10 MHz Reference Tune (0-2.5V)

Pictures & Construction Notes

Overview of a stock Stellex YIG synthesizer board.

The sampling microstripline directional coupler is on the upper-left.  The silver square in the middle is the MtronPTI K1526CMQA oscillator.  The United Monolithic CND2050 prescaler and National LMX2326 PLL are on the upper-right.  The Motorola TCA0372 op-amps are on the lower-left.

The 20-pin programming connector (gray) is on the middle-right.  The 6-pin connector (white) along the bottom is for connection to the YIG.

The pinout and description for the 6-pin Stellex miniYIG connector is:

Pin  YIG Wire Color    Description

1    Red               +8.5 VDC YIG Bias
2    Black             Ground
3    Violet            Tune +
4    Orange            Tune -
5    Yellow            FM +
6    Gray              FM -

Closeup of the sampling microstripline directional coupler with the SMA connectors removed.

The RF input from the YIG would be on the bottom connector.

R17 is a 3 dB attenuator pad and may be replaced with a 0603 size 0-ohm resistor.

R1 on the directional coupler output is a 0-ohm resistor on this version of the board.  It may be another attenuator on some models of this board.

Removing R17.

This is optional, but adds 3 dB to the final RF output signal.

Finished microstripline directional coupler overview.

R17 was replaced with a 0603 size 0-ohm resistor.

Beefing up the SMA connectors.

You should solder the SMA connectors (on the bottom of the board) to increase their mechanical stability.

This is handy when experimenting with the board so you don't break off the thin center of the SMA connector.

Overview of the 20-pin connector.

Note R24, a 1k ohm resistor.  This should be replaced with a 100 ohm resistor in order for the KE5FX programming software to reliably detect the locking of the LMX2326 PLL.

If you don't have a matching 20-pin connector, you may have to improvise something.

It helps to countersink the connector holes to allow for a little more working room.

It's possible to use the crimp pins from a DB-25 connector in the 20-pin connector.

The DB-25 crimp pins are a tight fit, but will work.

There is also a solder cup on the crimp pins to easily attach wires to the pins.

Inserting the crimp pins into the 20-pin connector.

Pins 5 & 6 are tied together, pins 15 & 16 are tied together, and all the grounds pins are tied together.  There is really no need to connect to all the pins.

Closeup of the stock 10 MHz MtronPTI K1526CMQA voltage-controlled oscillator.

You may want to use an external 10 MHz reference for a slight phase noise/jitter performance increase.

This will require disabling the stock MtronPTI K1526CMQ oscillator.  You can do this by removing R18, a 18-ohm resistor in series with the power line for the MtronPTI K1526CMQ oscillator.

To insert your new 10 MHz reference clock signal, you'll need to remove C28, a 1000 pF series coupling capacitor between the MtronPTI K1526CMQ oscillator and LMX2326 PLL.

After removing C28, drill a small hole to the side of the exposed solder pad going to the LMX2326.

This will allow for the center conductor of a small piece of coax carrying the external 10 MHz reference signal to connect to the solder pad.  This, in turn, is connected directly to pin-8 of the LMX2326.

Soldering the coax for the external reference signal.

Be sure the reference signal is well shielded and is isolated from the RF input to the PLL.

The Stellex YIG synthesizer module, Stellex 6755-726F miniYIG, and an external 10 MHz TCXO reference oscillator were mounted on a piece of K&S Metals aluminum sheet stock (#257).

An optional DB-25 connector allows for testing the YIG with the KE5FX software.  Be sure to remove the PIC if you use an external means of programming.

The pinout and description for the 25-pin parallel port connector is:

Pin      Description

2        LMX2326 Clock
3        LMX2326 Data
4        LMX2326 Load Enable
15       PLL Lock Detect
18-25    Ground

Overview of the finished Stellex YIG sythesizer and control board.

A Stellex 6755-726F miniYIG is shown on the upper-left.  Its tuning range is approximately 8.1 - 10.3 GHz (+/- 200 mA tuning current).  The synthesizer board will work with similar YIGs from around 2 GHz to over 12 GHz.

The RF output power from the synthesizer board was +5.6 dBm at 8.3 GHz and +3.5 dBm at 10 GHz.  Removing the R17 attenuator pad increases the output power by around 3 dB.  The raw RF output power from the YIG is around +12 dBm.

For this example, the PIC16F84 programs the YIG for either 8.37 GHz or 10.0 GHz, depending on the "Channel Select" switch position.


Stellex YIG Synthesizer Programming Notes

Refer to the National LMX2326 datasheet for a more detailed explanation of the latches.

The Stellex YIG synthesizer board is designed to be run in normal mode only.  The FastLock options are not usable.

The latches should be loaded in this order: Initialization Latch, Function Latch, R Counter, and N Counter.

The "Initialization Latch" really isn't required, but it's listed in the datasheet so load it anyway.

All the latches are programmed as a 21-bit shift register with the Most Significant Bit (MSB) first and on the rising edge of the clock signal.  Place the required value ("1" or "0") on the LMX2326's Data line then bring the Clock line high then back low.  Load the final 21-bit value into the PLL's latch by bringing the Load Enable line high then low.  All this can be accomplished by using the SHIFTOUT command under PICBasic.

Function and Intialization Latches

MSB                                                                   LSB
F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C2 C1
0   0   0   0   0   0   0   0   0   0   0  0  0  1  0  0  1  0  0  1  0

R Counter

Since the LMX2326 will be using a 10 MHz reference frequency and the step size needs to be 250 kHz, the "R Counter" will be 40.

This means the "32" and "8" bit divider ratios should be set to "1".

MSB                                                                   LSB
R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 C1
0   0   0   0   0   0   0   0   0   0   0  0  0  1  0  1  0  0  0  0  0

                    8   4   2   1   5   2  1  6  3  1  8  4  2  1
                    1   0   0   0   1   5  2  4  2  6
                    9   9   4   2   2   6  8
                    2   6   8   4

N Counter

This is the main divider ratio and swallow bit counter for the PLL.  For a YIG output frequency of 8370 MHz, the "N Counter" will need to be 8370 (8370 MHz divided by 4 from the prescaler, then divided again by the 250 kHz step size).  The LMX2326 PLL has an internal dual-modulus "divide-by-32" prescaler on its RF input, so the "N Counter" is actually divided into a separate "B Counter" and "A Counter."  The "B counter" will be 261 (integer of 8370 divided by 32) and the "A counter" will be 18.  This is the swallow counter value required to get 261 * 32 (8362) to equal 8370.

N = (32 * B) + A
B = div(N / 32)
A = N - (B * 32)

Where div(x) is defined as the integer portion and 32 is the prescaler value.

An example "N" value for the YIG at 8370 MHz: 8370 = (32 * 261) + 18

The "B Counter" will be 261.  This means the "256," "4," and "1" bit divider ratios should be set to "1".

The "A Counter" will be 18.  This means the "16" and "2" bit divider ratios should be set to "1".

MSB                                                                   LSB
N19 N18 N17 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 C2 C1
1   0   0   0   0   1   0   0   0   0   0  1  0  1  1  0  0  1  0  0  1
       
    4   2   1   5   2   1   6   3   1   8  4  2  1  1  8  4  2  1  
    0   0   0   1   5   2   4   2   6               6
    9   4   2   2   6   8
    6   8   4
    <-----------------B Counter------------------>  <-A Counter->




















Stellex YIG Synthesizer PICBasic Example Code

' Stellex YIG Oscillator Experiments
'
' LMX2326 Serial-Input PLL Frequency Synthesizer Loader Code
' PICBasic & 16F84
'
' LMX2326 DATA (12) = 16F84 PortB.1 (7)
' LMX2326 CLK (11)  = 16F84 PortB.0 (6)
' LMX2326 LE (13)   = 16F84 PortB.2 (8)
'
' Stellex 6755-726F YIG: 8.1 - 10.3 GHz
' Center Frequency: 9.14 GHz

IVAL1   VAR     WORD
IVAL2   VAR     BYTE
FVAL1   VAR     WORD
FVAL2   VAR     BYTE
RVAL1   VAR     WORD
RVAL2   VAR     BYTE
NVAL1A  VAR     WORD
NVAL2A  VAR     BYTE
NVAL1B  VAR     WORD
NVAL2B  VAR     BYTE

IVAL1 = $0004
IVAL2 = $13
FVAL1 = $0004
FVAL2 = $12
RVAL1 = $0005             ' R = 40 / 250 kHz step
RVAL2 = $0
NVAL1A = $8416            ' N = 8370 / 8.370 GHz
NVAL2A = $9
NVAL1B = $84E2            ' N = 10000 / 10.000 GHz
NVAL2B = $1               

Pause 20                  ' Wait a bit

POKE 134,128              ' PortB.0 - PortB.6 outputs, PortB.7 input

Low 0                     ' Bring CLK low
Low 1                     ' Bring DATA low
Low 2                     ' Bring LE low

' Load Initialization

SHIFTOUT 1,0,1,[IVAL1\16]        ' Data,Clock,Mode,[Bits]
SHIFTOUT 1,0,1,[IVAL2\5]
High 2                           ' Bring LE high, then low
Low 2            
Pause 3

' Load Function
SHIFTOUT 1,0,1,[FVAL1\16]
SHIFTOUT 1,0,1,[FVAL2\5]
High 2
Low 2
Pause 3






' Load /R
SHIFTOUT 1,0,1,[RVAL1\16]
SHIFTOUT 1,0,1,[RVAL2\5]
High 2
Low 2
Pause 3

'Load /N
IF (PortB.7 = 1) THEN
  SHIFTOUT 1,0,1,[NVAL1A\16]
  SHIFTOUT 1,0,1,[NVAL2A\5]
  High 2
  Low 2
  Pause 3
ELSE
  SHIFTOUT 1,0,1,[NVAL1B\16]
  SHIFTOUT 1,0,1,[NVAL2B\5]
  High 2
  Low 2
  Pause 3
ENDIF

Low 0                     ' Bring all pins low
Low 1
Low 2

End