Nortel DMS-100 Memory System Overview |
Introduction
This article presents a brief description of the memory devices used in the DMS-100 family of switches. The information provided applies to the DMS-100 NT40 central processor and the DMS SuperNode.
Memory Description
Memory, in this document, is a device used to store information in a form that enables the information to be easily and rapidly accessed when needed. In the DMS-100 family, the memory device most often used is the memory circuit pack or memory card where the information is encoded and stored electronically. This electronic storage is in the form of bits of information. A bit is a binary digit of 0 or 1. Bits are grouped together to form larger units called bytes or words. Each word represents a unit of information. Words may vary in length with bits forming 8-, 16-, and 32-bit words or larger. In the SuperNode system, the memory is organized into 40-bit words: 32 data bits, 7 error-correcting code bits, and 1 parity bit. Refer to the following Figure 1, which illustrates a 8-bit and a 16-bit word.
Figure 1 - Example of Bits and Words
Memory is measured in terms of the number of words or bytes that the device can store. Cards currently vary in size from 64k (k=1,024) words of memory to 1 M-word (1 million words) for data store and program store in the NT40 and 6-MBytes to 24-MBytes in the DMS SuperNode configuration. These sizes will probably change as the storage device technology evolves. The conversion of k-words to M-words to Mbytes is accomplished by dividing the k-words by the number 1,024 to get M-words and then multiplying the M-words by 2 to get Mbytes.
The bits, bytes, and words stored in memory make up the instructions, addresses, and other necessary data to operate the switch. The DMS-100 Central Processing Unit (CPU) controls and coordinates the operation of the peripheral modules, refer to Figure 2. Multitasking in real time is based upon processes that use messages to communicate with one another. These messages can be exchanged by the processes within the CPU, or they can be exchanged by the CPU processes and those in the peripheral modules.
In addition to the software necessary to provide the basic call processing decision functions, extensive software for the administration and maintenance of the DMS-100 hardware and connecting facilities is included. There are several thousand software modules consisting of several million lines of program code. To manage the design and production of reliable software on this scale, the system must have programming in a high-level language. The language used in the CPU is Procedure Oriented Type Enforcing Language (PROTEL), a high-level language developed by Bell-Northern Research (BNR).
Figure 2 - Functional View of a First Generation DMS-100
The NT40 Central Control Complex (CCC) is a totally duplicated group of four modules which act together to evaluate incoming messages, formulate proper responses, and issue instructions to the subsidiary units, see Figure 3.
The four modules are:
Figure 3 - Duplicated Central Control Complex
Duplication of the four CCC components offers hardware fault protection, and the ability to carry out office extensions and software updates without disrupting service.
The central processing unit, with associated program store and data store, is duplicated. Under normal circumstances, the two units operate in synchronism. Both are simultaneously executing the same instruction with the same data. Each has access to certain information in the mate CPU; therefore, fault detection for example, matching for loss of synchronism, can be carried out. In addition, this access provides interprocessor communication for system-maintenance software.
The CMC is duplicated, and the two components operate in load-sharing mode. That is, messages are routed alternately through the two CMC units.
CPU Memory Description
Memory within the CPU is divided into two distinct elements, each of which is independently addressable. These two elements are referred to as program store and data store.
Data store is divided into the following three regions:
These three regions are physically located in different parts of the DMS-100 but are on the same data bus and are accessed in the same manner. An address space distinguishes each of the three parts. The CPU RAM is located on the CPU card; data store is located on separate cards; and the I/O and maintenance registers are located in the CMC and in the CPU. The three regions of the data store are illustrated in Figure 4.
Figure 4 - Three Regions of Data Store
DMS SuperNode
The DMS-Core is the control component of SuperNode and consists of a Computing Module (CM) and a System Load Module (SLM). The computing module contains duplicated DMS SuperNode Central Processing Units (DMS SuperNode CPU).
Figure 5 - Functional View of a Second Generation DMS-100 (DMS SuperNode)
DMS SuperNode Memory
DMS SuperNode memory consists of memory circuit packs. Identical memory circuit packs are used, and memory is organized and addressed in the same manner in the computing module and in the message switch.
The memory consists of integrated program store and data store on the same bus. There are separate data and address buses, each 32-bits wide. Memory is byte addressable; thus, the logical address range is 4-Gigabytes.
Data Store
Data Store Hardware - NT40
The NT40 Data Store (DS) shelf has sixteen card slots available for the active data store plus one card slot used as a memory controller. This controller card has 256k words of memory to be used as replacement memory for detected single memory faults in any of the memory cards. Memory cards come in different sizes. For example, the NT3X93 (256k words) and the NT4X80 (1-Mwords).
This shelf has a maximum capacity of 15k to 15.75k words of addressable storage depending upon the central control complex vintage. The rest is reserved for system use, for example, write-protected registers.
Another memory card, which may be present in existing NT40 switches, is the NTX3X40. This card contains 64k words of memory.
Data Store Hardware - DMS SuperNode
Data store and program store are integrated. Memory is provided on memory circuit packs, and there are two types:
Addressing
To determine where information resides in the NT40, the DS uses an address consisting of a 8-bit page and a 16-bit offset. Each page of DS contains 64k (65,536) words. For example, #FB12A4 is an address on page #FB with an offset of #12A4 words from the beginning of the page.
The DMS SuperNode uses an address consisting of a 16-bit page and a 16-bit offset. Each page of DS contains 16-Mwords.
Bits within a word of data store are addressed by a number from 0-15, from the least significant bit to the most significant bit. The least significant bit is the bit at the low address end of the word. For example, number 8004 would be represented by setting all of the bits within a word to zero except for bits 15 and 2, which are set to one. The numbering of bits within a word (for example, 8004) is illustrated in Figure 6.
Figure 6 - Bit Numbering
Data Store Tables
The DMS-100 data store is comprised of many different data tables containing information required to complete connections between calling and called parties. A table consists of a number of objects of the same type, occupying a contiguous segment of memory in date store, so that each entry in the table may be indexed (located). An illustration of a NT40 table with six entries, four words in length, is shown in Figure 7.
Figure 7 - NT40 Data Store Tables
The following figure is an illustration of a DMS SuperNode table with six entries, eight words in length.
Figure 8 - DMS SuperNode Data Store Tables
Pointers and Descriptors
A descriptor is a three-word (for the NT40) or a four-word (for the DMS SuperNode) code that describes a table or a part (slice) of a table. The individual entries in a table are addressed by indexing the descriptor as if it were a table. A descriptor contains the following information for the NT40:
A descriptor for the DMS SuperNode contains the following information:
In normal usage it is not necessary to know the internal layout of a descriptor, since these parts are not separately manipulated. See Figure 9 for an illustration of a pointer, a descriptor, and a table.
Figure 9 - Example of a Pointer, a Table, and a Descriptor
Dynamic Allocation of Data Store
The DMS-100 operating system allows data store to be managed as a common resource pool. This pool makes it possible for executing programs to allocate (request) store from the unused parts of data store. When this allocated storage is no longer required, it is deallocated (returned) to the common pool for use by other executing programs. Programs that allocate and deallocate tables in the data store use descriptors to store the location and size of these dynamic tables. Pointers can also be used to allocate tables of a fixed size. The fact that PROTEL can dynamically allocate data store has a very important implication: the size of data tables does not have to be decided at design time or at compile time.
Types of Data Store
The following types of data store are in the DMS-100 switch:
It is the design requirement of a program that determines what store types are used. The low end of memory (CPU RAM) and the high end of memory which is reserved for I/O and maintenance registers are not assigned a data store type and are not allocated by the store allocator.
Protected Data Store
Protected Data Store (DSPROT) is used to define such elements as office configuration, what directory numbers are attached to what lines, and routing tables. Typically, DSPROT changes only in response to a user interface command and is used for constant data.
The DSPROT has hardware write protection and must have the protection removed prior to any write operations. The DSPROT remains allocated, and its contents unchanged over warm and cold restarts. Descriptions of restarts are located at the end of this article.
The CPU RAM Store (DSRAM) is cleared and deallocated on reload restarts. The DSSAVE, which includes information about what caused the previous restart, is not cleared on any type of restart, even when a different software load is installed.
Permanent Data Store
Permanent Data Store (DSPERM) is a memory area that does not have hardware write protection. The DSPERM remains allocated over all restarts, but the contents must be reinitialized after a restart reload.
This area is used to hold control information and long-term statistical information. Examples of control information include shared variables, call information, and the state (free or busy) of the different input/output devices. Examples of long-term statistical information include operational measurements, call statistics, and log report data.
Although the contents of DSPERM survive both cold and warm restarts, the area that is used for control information is normally reinitialized after all restarts except warm.
Temporary Data Store
Temporary Data Store (DSTEMP) does not have hardware write protection. The DSTEMP is deallocated and the contents cleared after every restart.
The DSTEMP area is used for short-term, transient data (for example, data necessary to execute a program and local variables for a procedure call).
DSSAVE Data Store
The DSSAVE Data Store area's page one remains allocated and unchanged over all restarts, even when a new software load is installed. Therefore, it can be used to store information over reload restarts. There is no hardware write protection on DSSAVE.
DSRAM Data Store
The DSRAM Data Store area remains allocated and unchanged over warm and cold restarts. On reload restarts, it is deallocated by the system. It is used by selected applications that need rapid memory capabilities.
Program Store
Program Store Hardware - NT40
The program store contains the instructions required by the associated CPU for call processing, maintenance, and administrative tasks. The NT40 central processor and memory shelf has eight card slots available for active program store plus one card slot used as a memory controller. This controller card has 256k of memory to be used as replacement memory when a detected single fault occurs in any one of the memory cards. The memory cards come in different sizes, for example, the NT3X93 (256k words) and the NT4X80 (1-Mwords.)
Program Store Hardware - DMS SuperNode
Data store and program store are integrated. Memory is provided on two types of memory circuit packs:
Program Store Organization
The NT40 program store address consists of an 8-bit page and a 16-bit offset. Each page of program store contains 64k (65,536) bytes. For example, #1FA2B4 is an address on page 1F, with an offset of A2B4 bytes from the beginning of the page.
The DMS SuperNode uses an address consisting of a 16-bit page and a 16-bit offset. Each page of DS contains 16-Mwords.
Bits within a byte of program store are addressed by number from 7-0, from the most significant bit to the least significant bit. The numbering of bits within a byte is illustrated in Figure 10.
Figure 10 - Program Store Bit Numbering
Pointers and Descriptors
Program store procedure descriptors are located in the protected data segment of the module. They are used to point to procedures stored in the program store.
Dynamic Allocation of Program Store
Only the loader and some debugging tools allocate program store. The same utilities and methods used to allocate data store are used to allocate program store.
Protected Program Store
Protected program store has hardware write protection. All permanent programs are loaded into PSPROT. Program store survives all restarts.
Store Allocation
The Support Operating System (SOS) allocator manages the allocation and deallocation of all memory in the CC. It handles both data store and program store. When the store allocator undergoes initial program loading initialization, all of the data store and program store are divided up into areas of memory known as vast areas. For all types of data store except DSRAM and DSSAVE, vast areas range in size from 16k words to 32k words. For DSRAM and DSSAVE, vast areas can be up to 32k words, with no minimum size. Program store vast areas have 32k bytes.
Initially, vast areas do not have a type associated with them. As allocation requests are made, vast areas are set to the type required, which can be one of the following: DSTEMP, DSPERM, DSPROT, DSSAVE, DSRAM, PSTEMP, and PSPROT.
Vast areas also have an associated status that indicates if the area is available to be allocated as any store type (designated as available) or if it is already in use as a specific type (designated as in use).
Store is allocated in contiguous segments, known as store blocks, which may be any size up to the size of a vast area. Header tables are maintained to keep track of the allocated vast areas and of the store blocks that are allocated within the vast areas.
Store Allocation Lists
The store allocator checks to ensure that all allocations of store remain within the limits of one vast area. When store is deallocated, it is entered into the list of free store for that vast area. Adjacent free store blocks are concatenated (linked together). Blocks of store cannot be partially deallocated; therefore, half of a block of store cannot be deallocated. On restarts, vast areas of type DSTEMP are set to a status of available.
Segmented Store
The segmented store utility is provided to allow the store allocation of variable-size tables. Use of the segmented store allows large tables to be extended without the need to copy or change the store already allocated. Segmented store also allows the allocation of tables larger than a vast area.
Segmented store allows a conceptually contiguous table of store to be physically distributed in noncontiguous blocks of store. All the blocks are the same size. It uses a two-level table and is implemented in the module SEGSTOR. The table can have up to 64k items, the addressing range of a 16-bit word.
SuperNode
The DMS SuperNode is part of a second generation of the DMS-100 switch in which the DMS SuperNode replaces the NT40 central processor. There are some DMS SuperNode and the NT40 similarities, for example, both of the control component CPU memory areas consist of two distinct elements, program store and data store. Program store contains variable-length program instructions. Data store contains data. At the same time, one of the most significant differences in the two control components is memory. A comparison of the memory attributes of both switch generations is summarized in the following table:
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Comparison of Memory - NT40 and SuperNode
Memory Attribute Central Control CPU DMS SuperNode CPU
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Addressing Unit
Program Store Byte addressable Byte addressable
Data Store Word addressable Byte addressable
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Address Bus Width 24 bits 24 bits
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Address Range Combined program store and data
store: 4 gigabytes
Program Store 16 megabytes
Data Store 16 megawords
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Data Bus Width 16 bits 32 bits
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Page Size
Program Store 64 kilobytes 64 kilobytes
Data Store 64 kilowords 64 kilobytes
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Vast Area Size
DSRAM Up to 32 kilowords 12 kilobytes
DSSAVE Up to 32 kilowords 32 or 64 kilobytes
OTHER Data Store 16 to 32 kilowords 32 or 64 kilobytes
Program Store 32 kilobytes 32 or 64 kilobytes
RAM68DT N/A 20 kilobytes
RAM68PP N/A 32 kilobytes
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-End-
A DMS SuperNode has ten card slots available for memory on the DMS-Core shelf. The program store and data store memory in a SuperNode configuration is pooled in that the memory cards can be used for either of the two stores, and there is no physical separation of the two stores as there is in the NT40. However, once the memory has been designated as one store or the other, it can only be used for that store until the designation has been changed.
There are two different memory cards available:
There are recommended mixed memory card configurations when the initial DMS-SuperNode installation provides only 6-MByte cards and a memory extension job is required. Refer to the following table:
----------------------------------------------------------------------------------------- Recommended Mixed Memory Card Configurations Total MBytes Active Plus Required Administrative 6 MByte 24 MByte 6 MByte 24 MByte Spare Cards Cards Spare Cards Spare Cards ---------------------------------------------------------------------------------------- 0-42 7 0 1 0 42-48 8 0 1 0 48-54 9 0 1 0 54-60 7 1 1 1 60-80 6 2 1 1 84-100 5 3 1 1 10-116 4 4 1 1 11-132 3 5 1 1 12-156 2 6 1 1 16-168 1 7 1 1 168-212 0 9 0 0 ---------------------------------------------------------------------------------------- -End-
Vast Areas
Vast area sizes for each store type are shown in the previous figure. For SuperNode DSRAM, the vast area size is 12-kilobytes. For RAM68DT, it is 20-kilobytes; for RAM68PP, it is 32-kilobytes. For all other types of data store and program store, the vast area size is 32-kilobytes or 64-kilobytes. Vast areas are initially allocated with a size of 64-kilobytes. If less than half of a vast area is used at initial program load time, the store allocator splits the 64-kilobyte vast area into two 32-kilobyte vast areas. Both of these 32-kilobyte areas are of the same store type since they reside on the same 64-kilobyte page of memory. The store allocator reserves the unused 32-kilobyte vast area until some of its assigned type is required.
The store allocator cannot allocate blocks of store larger than the size of a vast area. Thus, for all types of data store, except DSRAM, data structures cannot have more than 64-kilobytes of contiguous store. Larger structures are accommodated by segmenting the structure into blocks of 64-kilobytes or less. However, procedures cannot be segmented; therefore, they cannot be larger than 64-kilobytes in size (32-kilobytes in RAM68PP).
Fragmented Memory
Fragmented memory is the deallocated memory within "INUSE" vast areas that has no data to be assigned to its free blocks; that is, the memory was deallocated, but no additional requests were made that would fit into its space. Therefore, there are holes in the used memory areas. The available blocks of memory that make up the holes may be recovered by either a cold restart or by the dump and restart process when the allocator finds a block of data that fits into the hole. In the engineering process, the provisioning formula provides an additional eight percent of memory in data store to compensate for fragmentation.
The DSTEMP memory can be made available by a warm restart while DSPROT memory can be overwritten by a dump and restore (new software load). The DSRAM memory can be made available by a restart reload.
An accurate status of the switch memory areas may be obtained through the MAP Command Interpreter (CI) utility, STORE AREAS, which displays a complete listing of all vast area memory allocation. Memory addresses are presented in hexadecimal form, and a total free hexadecimal representation of all free data store or program store is displayed at the bottom of the listing.
Determining fragmented memory (in bytes) for the NT40 may be accomplished using the MAP CI utility, STORE AREAS, and can be calculated by following the steps in the following procedure:
Total Free - (End Avail - Start Avail)
% Fragmentation = -------------------------------------- x 100
(End Avail - Start In Use)
Program store memory fragments very little. Sufficient program store is provided for approximately one year of source code, in accordance with current NT software administration policy.
Restarts
A restart is an ordered initialization of every module in the system. Restarts serve two important purposes.
There are four types of restart: warm, base, cold, and reload.
Warm Restart
A warm restart is the least severe type of restart. Temporary Data Store (DSTEMP) is cleared and deallocated. All other types of store survive a warm restart.
Base Restart
A variation of a warm restart, the base restart is used to debug initialization code during the software development process. A base restart is a drastic measure. It disables the system's call processing capability and, therefore, should never be performed in a system that is operational.
Cold Restart
A cold restart is more severe than a warm restart. DSPERM survives a cold restart, but its contents are suspect since some programs cause automatic cold restarts if their DSPERM appears to be corrupted. For this reason, many modules reinitialize DSPERM on cold restarts. A cold restart has all of the effects of a warm restart, plus additional effects due to the reinitialization of data in DSPERM.
Call processing is affected by the reinitialization of the data in DSPERM in which the following events occur:
Calls in progress that have reached the talking state retain their switching network connections during the restart, but they may be disconnected if their switching network paths are reused by new calls after the restart. There is no record of the call's existence in the CC; the only call processing function that can be performed is call take-down. No billing data are recorded for these calls.
Reload Restarts
A reload restart is even more severe than a cold restart. It has all the effects of a cold restart; in addition, DSPERM is cleared but remains allocated. The DSRAM is cleared and deallocated on reload restarts. The DSSAVE, which includes information about what caused the previous restart, is not cleared on any type of restart, even when a different software load is installed.