Hi all
Do you ever tried to create a critical section on your ASM code? I mean a
critical section that is not using Windows APIs.
A simple approach is this(assume eax is initialize by 0 somewhere):

here:
cmp eax,0
jne here
mov eax,1
<critical section>
mov eax,0

(This code still have some problems that there is a posiblity of concurrent access,but my problem is not that for now)

My problem is that this algorith use a busy waiting loop that decrease code performace too much.
I wana know is there anyway to make a critical section that solved busy waiting problem in ASM?
Remember that "Pause" Asm code is designed only for P4 and not woking at P3.

Regards

You could write your own user-mode thread scheduler so that you can use synchronization objects without using OS API. But I don't know why the hell you wouldn't want to just call the API functions.. that's what they're there for.

It is not that I can't Use APIs, But because it makes some trouble for me, I only want to check if it is possible to do it only using ASM or not.

Regards

No. Thread synchronising (if that's what you're trying to do) is handled by OS. Unless you write own scheduler and microthreads...

Check this.
http://en.wikipedia.org/wiki/Spinlock#Example_implementation

No, he doesn't want to use a spinlock. That's what he's using right now. He wants his thread to sleep (not spin) until the synchronization object is free and be notified at that point.

I don't think that's possible without using API...

Yea,it is exactly what you said.
But I should say,if it was P4 processor,there is an "Pause" code that will create a situation like sleeping threads when it is used in a implementation of spin lock,then that spin like will become like what i need.
The problem is that this command is only added stating from P4....

Regards

Just use the lock semantic when acquiring access to your semaphore or use xchg that implicitly performs a lock.

If you are not on P4+, pause will behave as a NOP for the processor, thus it can run on every processor. drawback is, in that case the spinloop will eat CPU quantum of a waiting thread running the spinloop.

repz nop

by the way, you can also call sleep(0) in the spin loop to increase the overall performance.
Lock+Pause or Lock+Sleep(0) should either do it.

But his thread would still be scheduled and would still consume cycles. You need the OS to know to not schedule your thread if you want to avoid spinning, and to do this you should use the API functions.

Just use the API man, the O.S. schedules threads, and it's the O.S. you need to talk to, period. Unless you want to virtualize your whole app.

-nt20

Hello, the question here is if it's possible to optimize a spinlock without using a schedular (or some refer to as OS APIs). The answer is not efficiently.

On OS with pre-emptive kernels such as most Windows and Linux kernels, high priority process/thread can preempt low priority task that is spending most of its time busy looping in a spinlock. By moving such a low priority task to sleep state, the kernel is effectively optimizing cpu use. You will notice your UP system is a little slower but it's still quite usable. The reason for the slowdown is that the spinlock thread is simply not very cooperative and does not yield cpu time.

Another factor to consider is SMP. On multi processor machine, such a busy loop process is usually bound to a particular cpu and user can hardly notice any kind of system slowdown for interactive work. This is a very easy experiment to try out.

Is there room for a little bit optimization on SMP system? Check out 'lock xchg'. The memory subsystem will kick in and block such a thread from execution until the bus is locked to synchronize this memory value between multiple CPUs.

Note that such looping takes a large amount of energy from the power supply.

For example, execute an eb fe loop process and measure the temperature increase.

repz nop doesnt do that, its how windows does its spinlocks etc...

Unfortunately whether repz nop can reduce cpu load or not is highly architecture dependent. Only certain families of IA32 cpus support this feature.