Maybe this topic, I just posted, seams unappropriate in this forum.
Although it resambles a hardware reverse engeenear issue, it could easly be found in a software implementation too.
Im talking about reversing an unknown crypto cipher, implemented in a chip.
I was wondering what type of algorithm this cipher uses. Whether it is a block or a stream cipher. As far as I know it could be both, but I must say that my knowledge in hardware implementation of crypto ciphers is not so good. Therefor I ask your opinion, and maybe your colaboration in reversing it.
The cipher works like this:
- it's response-challenge based
- challenge = 6 random bytes (that you provide)
- response = 2 bytes (generated by the algorithm)
- key = 6 bytes (48-bits)

Code:
ATR; // card is reseted, and it outputs the first bit from memory (512bits long)
FOR 1 to 110 Pulse_CLK; // Pulse CLK till the 111th bit}
Pulse_RST
Pulse_CLK // Write to bit 111
FOR 1 to 177 do Pulse_CLK // Provides the cipher with data
128 bit DATA + 48 bit KEY = 177 (as far as I see it)
FOR 1 to 48 do // send the 48bit challenge
set bit 1..48 of challenge
Pulse_CLK
EndFor
FOR 1 to 8 do // Read output
FOR 1 to 160 do Pulse_CLK;
readOutputBIT;
So...
The Algorithm needs 177 clocks to initialize + 48bit of challenge
And then it outputs one bit after every 160 clock cycles.

I wonder what could it be. A delayed stream cipher or a block cipher (a hash alg. like this could be implemented in both ways).
Any of you guys keen in crypto hardware that could give me an answer please feel free. Other ideeas of reversing this are also wellcomed.
Thanks