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54ABT646  Product Folder

Octal Transceivers and Registers with TRI-STATE Outputs
General
Description
Features Datasheet Package
& Models
Samples
& Pricing

Parametric Table Parametric Table
Temperature Min (deg C) -55 
Temperature Max (deg C) 125 

Datasheet

TitleSize in KbytesDate
View Online

Download

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54ABT646 Octal Transceivers and Registers with TRI-STATE Outputs 319 Kbytes 6-Aug-98 View Online Download Receive via Email
54ABT646 Mil-Aero Datasheet MN54ABT646-X 18 Kbytes   View Online Download Receive via Email

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Package Availability, Models, Samples & Pricing

Part NumberPackageStatusModelsSamples &
Electronic
Orders
Budgetary PricingStd
Pack
Size
Package
Marking
TypePinsMSL/Lead-Free AvailabilityLead
Time
QtySPICEIBISQty$US each
5962-9457701Q3A
(54ABT646E-QML)
LCC28StatusFull productionN/AN/A 50+$11.50tray
of
25
NSZSSXXYYA
54ABT646E
-QML
5962-
9457701Q3A
9-11 weeks500
5962-9457701QLA
(54ABT646J-QML)
CERDIP24StatusFull productionN/AN/A 50+$8.25rail
of
15
NSZSSXXYYA>
54ABT646J-QML
5962-9457701QLA
8-10 weeks500
5962-9457701QKA
(54ABT646W-QML)
CERPACK24StatusFull productionN/AN/A 50+$11.50rail
of
19
NSZSSXXYYA>
54ABT646W-QML
5962-
9457701QKA
9-11 weeks500

General Description

The 'ABT646 consists of bus transceiver circuits with TRI-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control OE# and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control OE# is Active LOW. In the isolation mode (control OE# HIGH), A data may be stored in the B register and/or B data may be stored in the A register.

Features

  • Independent registers for A and B buses
  • Multiplexed real-time and stored data
  • A and B output sink capability of 48 mA, source capability of 24 mA
  • Guaranteed multiple output switching specifications
  • Output switching specified for both 50 pF and 250 pF loads
  • Guaranteed simultaneous switching noise level and dynamic threshold performance
  • Guaranteed latchup protection
  • High impedance glitch free bus loading during entire power up and power down cycle
  • Nondestructive hot insertion capability
  • Standard Microcircuit Drawing (SMD) 5962-9457701
[Information as of 15-Jan-2004]