CLC5957 Product Folder |
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| General Description |
Features | Datasheet | Package & Models |
Samples & Pricing |
Reliability Metrics |
Application Notes |
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| Title | Size in Kbytes | Date | View Online |
Download |
Receive via Email |
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| CLC5957 12-Bit, 70 MSPS Broadband Monolithic A D Converter | 1669 Kbytes | 26-Apr-02 | View Online | Download | Receive via Email |
| CLC5957 12-Bit, 70 MSPS Broadband Monolithic A D Converter (JAPANESE) |
1146 Kbytes |
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| Part Number | Package | Status | Models | Samples & Electronic Orders | Budgetary Pricing | Std Pack Size | Package Marking | |||||
| Type | Pins | MSL/Lead-Free Availability | Lead Time | Qty | SPICE | IBIS | Qty | $US each | ||||
| CLC5957PCASM | evaluation board | Full production | N/A | N/A | | 1+ | $176.00 | 1 | - | |||
| N/A | 0 | |||||||||||
| CLC5957MTD | TSSOP | 48 | Status | Full production | N/A | N/A | 1K+ | $19.10 | rail of 38 | NSUZXYTT CLC5957MTD | ||
| 18 weeks | 0 | |||||||||||
| CLC5957MTDX | TSSOP | 48 | Status | Full production | N/A | N/A | 1K+ | $19.10 | reel of 1000 | NSUZXYTT CLC5957MTD | ||
| 18 weeks | 0 | |||||||||||
The CLC5957 is a monolithic 12-bit, 70MSPS analog-to-digital converter. The device has been optimized for use in IF-sampled digital receivers and other applications where high resolution, high sampling rate, wide dynamic range, low power dissipation, and compact size are required. The CLC5957 features differential analog inputs, low jitter differential universal clock inputs, a low distortion track-and-hold with 0-300MHz input bandwidth, a bandgap voltage reference, data valid clock output, TTL compatible CMOS (3.3V or 2.5V) programmable output logic, and a proprietary 12-bit multi-stage quantizer. The CLC5957 is fabricated on the ABIC-V 0.8 micron BiCMOS process. The CLC5957 features a 74dBc spurious free dynamic range (SFDR) and a 67dB signal to noise ratio (SNR). The wideband track-and-hold allows sampling of IF signals to greater than 250MHz. The part produces two-tone, dithered, SFDR of 83dBFS at 75MHz input frequency. The differential analog input provides excellent common mode rejection, while the differential universal clock inputs minimize jitter. The 48-pin TSSOP package provides an extremely small footprint for applications where space is a critical consideration. The CLC5957 operates from a single +5V power supply. Operation over the industrial temperature range of -40°C to +85°C is guaranteed. National Semiconductor tests each part to verify compliance with the guaranteed specifications. |
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| Part Number | Process | Early Failure Rate - Rejects | Sample Size (EFR) | PPM * | Rel. Rejects | Device Hours | Long Term Failure Rates (FITS) | MTTF |
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| CLC5957MTDX | ABIC | 4 | 12000 | 334 | 0 | 750000 | 5 | 212054006 |
| CLC5957MTD | ABIC | 4 | 12000 | 334 | 0 | 750000 | 5 | 212054006 |
| Title | Size in Kbytes | Date | View Online |
Download |
Receive via Email |
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| CLC-EDRCS-PCASM: CLC-EDRCS-PCASM EDRCS Evaluation Board User's Guide | 2275 Kbytes | 12-Oct-01 | View Online | Download | Receive via Email |
| CLC-DRCS7-PCASM: CLC-DRCS7-PCASM DRCS7 Evaluation Board User's Guide | 2140 Kbytes | 1-Feb-01 | View Online | Download | Receive via Email |
| CLC5526: CLC5526/CLC5956/CLC5902 Diversity Receiver Chipset | 406 Kbytes | 2-Oct-00 | View Online | Download | Receive via Email |
| CLC5902: CLC5526/CLC5956/CLC5902 Diversity Receiver Chipset | 406 Kbytes | 2-Oct-00 | View Online | Download | Receive via Email |
| CLC5956: CLC5956 12-Bit[comma] 65 MSPS Broadband Monolithic A/D Converter | 406 Kbytes | 19-Jan-01 | View Online | Download | Receive via Email |
| CLC5956 12-Bit[comma] 65 MSPS Broadband Monolithic A/D Converter (JAPANESE) |
423 Kbytes | ||||
| DRCS: CLC5526/CLC5956/CLC5902 Diversity Receiver Chipset | 406 Kbytes | 2-Oct-00 | View Online | Download | Receive via Email |
| WIRELESS_BASE_STATION: Wireless Base Station Evaluation Board Interoperability Guide | 1365 Kbytes | 16-Oct-00 | View Online | Download | Receive via Email |
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If you have trouble printing or viewing PDF file(s), see Printing Problems. |
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