DM5474 Product Folder |
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| General Description |
Features | Datasheet | Package & Models |
Samples & Pricing |
| Title | Size in Kbytes | Date | View Online |
Download |
Receive via Email |
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| 5474 DM5474 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs | 121 Kbytes | 6-Jan-98 | View Online | Download | Receive via Email |
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If you have trouble printing or viewing PDF file(s), see Printing Problems. |
| Part Number | Package | Status | Models | Samples & Electronic Orders | Budgetary Pricing | Std Pack Size | Package Marking | |||||
| Type | Pins | MSL/Lead-Free Availability | Lead Time | Qty | SPICE | IBIS | Qty | $US each | ||||
| DM5474W/883 | CERPACK | 14 | Status | Lifetime buy | N/A | N/A | 50+ | $5.25 | rail of 19 | NSZSSXXYYA> DM5474W /883QL | ||
| 10-12 weeks | 500 | |||||||||||
| DM5474W-MLS | CERPACK | 14 | Status | Lifetime buy | N/A | N/A | rail of N/A | NSZSSXXYYA DM5474W- MLS > | ||||
| N/A | 0 | |||||||||||
| Obsolete Part | Alternate Part or Supplier | Source | Last Time Buy Date |
|---|---|---|---|
| DM5474J/883 | 5474 | ROCHESTER | 12/02/2003 |
| DM5474W-MLS | 5474 | ROCHESTER | 03/03/2004 |
| DM5474W-MLS | 7510 | ROCHESTER | 03/03/2004 |
| DM5474W-MLS | ML5474 | LANSDALE SEMICONDUCTOR INC | 03/03/2004 |
| DM5474W-MLS | SL5474 | LANSDALE SEMICONDUCTOR INC | 03/03/2004 |
| DM5474W-MLS | SL8828 | LANSDALE SEMICONDUCTOR INC | 03/03/2004 |
| DM5474W/883 | 5474 | ROCHESTER | 03/03/2004 |
| DM5474W/883 | 7510 | ROCHESTER | 03/03/2004 |
| DM5474W/883 | ML5474 | LANSDALE SEMICONDUCTOR INC | 03/03/2004 |
| DM5474W/883 | SL5474 | LANSDALE SEMICONDUCTOR INC | 03/03/2004 |
| DM5474W/883 | SL8828 | LANSDALE SEMICONDUCTOR INC | 03/03/2004 |
This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is low or high without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. |
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