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DP83932C-25  Product Folder

MHz SONIC Systems-Oriented Network Interface Controller [Life-time buy]
Generic P/N 83932C-25
General
Description
Features Datasheet Package
& Models
Samples
& Pricing
Reliability
Metrics

Datasheet

TitleSize in KbytesDate
View Online

Download

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DP83932C-20 25 33 MHz SONIC(TM) Systems-Oriented Network Interface Controller 1092 Kbytes 24-Mar-97 View Online Download Receive via Email

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Package Availability, Models, Samples & Pricing

Part NumberPackageStatusModelsSamples &
Electronic
Orders
Budgetary PricingStd
Pack
Size
Package
Marking
TypePinsMSL/Lead-Free AvailabilityLead
Time
QtySPICEIBISQty$US each
DP83932CVF-25PQFP132StatusLifetime buyN/AN/A 250+$33.80tray
of
36
UZXXYYTT
PATENTED
C M
DP83932CVF-25
8 weeks0

General Description

The SONIC (Systems-Oriented Network Interface Controller) is a second-generation Ethernet Controller designed to meet the demands of today's high-speed 32- and 16-bit systems. Its system interface operates with a high speed DMA that typically consumes less than 3% of the bus bandwidth (25 MHz bus clock). Selectable bus modes provide both big and little endian byte ordering and a clean interface to standard microprocessors. The linked-list buffer management system of SONIC offers maximum flexibility in a variety of environments from PC-oriented adapters to high-speed motherboard designs. Furthermore, the SONIC integrates a fully-compatible IEEE 802.3 Encoder/Decoder (ENDEC) allowing for a simple 2-chip solution for Ethernet when the SONIC is paired with the DP8392 Coaxial Transceiver Interface or a 10BASE-T transceiver.

For increased performance, the SONIC implements a unique buffer management scheme to efficiently process, receive and transmit packets in system memory. No intermediate packet copy is necessary. The receive buffer management uses three areas in memory for (1) allocating additional resources, (2) indicating status information, and (3) buffering packet data. During reception, the SONIC stores packets in the buffer area, then indicates receive status and control information in the descriptor area. The system allocates more memory resources to the SONIC by adding descriptors to the memory resource area. The transmit buffer management uses two areas in memory: one for indicating status and control information and the other for fetching packet data. The system can create a transmit queue allowing multiple packets to be transmitted from a single transmit command. The packet data can reside on any arbitrary byte boundary and can exist in several non-contiguous locations.

Features

  • 32-bit non-multiplexed address and data bus
  • High-speed, interruptible DMA
  • Linked-list buffer management maximizes flexibility
  • Two independent 32-byte transmit and receive FIFOs
  • Bus compatibility for all standard microprocessors
  • Supports big and little endian formats
  • Integrated IEEE 802.3 ENDEC
  • Complete address filtering for up to 16 physical and/or multicast addresses
  • 32-bit general-purpose timer
  • Full-duplex loopback diagnostics
  • Fabricated in low-power CMOS
  • 132 PQFP package
  • Full network management facilities support the 802.3 layer management standard
  • Integrated support for bridge and repeater applications

Reliability Metrics

Part Number Process Early Failure Rate - Rejects Sample Size (EFR) PPM * Rel. Rejects Device Hours Long Term Failure Rates (FITS) MTTF
DP83932CVF-25CS10031940015509000004254464808

For more information on Reliablitity Metrics, please click here.


[Information as of 15-Jan-2004]