DS1776 Product Folder |
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| General Description |
Features | Datasheet | Package & Models |
Samples & Pricing |
Application Notes |
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| Title | Size in Kbytes | Date | View Online |
Download |
Receive via Email |
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| DS1776 PI-Bus Transceiver | 204 Kbytes | 12-Jul-99 | View Online | Download | Receive via Email |
| DS1776 Mil-Aero Datasheet MNDS1776-X | 17 Kbytes | View Online | Download | Receive via Email |
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If you have trouble printing or viewing PDF file(s), see Printing Problems. |
| Part Number | Package | Status | Models | Samples & Electronic Orders | Budgetary Pricing | Std Pack Size | Package Marking | |||||
| Type | Pins | MSL/Lead-Free Availability | Lead Time | Qty | SPICE | IBIS | Qty | $US each | ||||
| 5962-9231701M3A | LCC | 28 | Status | Full production | N/A | N/A | 50+ | $98.00 | tray of 25 | NSZSSXXYYA DS1776E /883QL > 5962- 9231701M3A | ||
| 8-10 weeks | 500 | |||||||||||
| DS1776 MD8 | Unpackaged Die | Full production | N/A | N/A | tray of N/A | - | ||||||
| N/A | 0 | |||||||||||
| DS1776 MW8 | Wafer | Full production | N/A | N/A | wafer jar of N/A | - | ||||||
| N/A | 0 | |||||||||||
The DS1776 is an octal PI-bus Transceiver. The A to B path is latched. B outputs are open collector with series Schottky diode, ensuring minimum B output loading. B outputs also have ramped rise and fall times (2.5 ns typical), ensuring minimum PI-bus ringing. B inputs have glitch rejection circuitry, 4 ns typical. Designed using National's Bi-CMOS process for both low operating and disabled power. AC performance is optimized for the PI-Bus inter-operability requirements. The DS1776 is an octal latched transceiver and is intended to provide the electrical interface to a high performance wired-or bus. This bus has a loaded characteristic impedance range of 20 Ohm to 50 Ohm and is terminated on each end with a 30 Ohm to 40 Ohm resistor. The DS1776 is an octal bidirectional transceiver with open collector B and TRI-STATE A port output drivers. A latch function is provided for the A port signals. The B port output driver is designed to sink 100 mA from 2V and features a controlled linear ramp to minimize crosstalk and ringing on the bus. A separate high level control voltage (VX) is provided to prevent the A side output high level from exceeding future high density processor supply voltage levels. For 5V systems, VX is tied to VCC. |
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| Title | Size in Kbytes | Date | View Online |
Download |
Receive via Email |
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| AN-725: Application Note 725 PI Bus | 63 Kbytes | 5-Oct-98 | View Online | Download | Receive via Email |
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If you have trouble printing or viewing PDF file(s), see Printing Problems. |
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