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DS90C383  Product Folder

+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
  

See Also:
  
DS90C383A - improved timing specs
Generic P/N 90C383
General
Description
Features Datasheet Package
& Models
Samples
& Pricing
Reliability
Metrics
Application
Notes

Parametric Table Parametric Table
Temperature Min (deg C) -10 
Temperature Max (deg C) 70 
Supply Voltage (Volt) 3.30 
Pixel Clock Rate (MHz) 65 
Graphic Bits (bit)
DisplayType FPD 
Strobe Edge Programmable 
Function Transmitter 

Datasheet

TitleSize in KbytesDate
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DS90C383 DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz 365 Kbytes 14-Nov-00 View Online Download Receive via Email
DS90C383 DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz (JAPANESE)
220 Kbytes   View Online Download Receive via Email

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Package Availability, Models, Samples & Pricing

Part NumberPackageStatusModelsSamples &
Electronic
Orders
Budgetary PricingStd
Pack
Size
Package
Marking
TypePinsMSL/Lead-Free AvailabilityLead
Time
QtySPICEIBISQty$US each
DS90C383MTDTSSOP56StatusFull productionN/A90c383.ibs24 Hour Samples
Buy Now
1K+$3.50rail
of
34
NS2ZXYTT
DS90C383MTD
BBBBB
3-9 weeks2000
DS90C383MTDXTSSOP56StatusFull productionN/AN/A 
Buy Now
1K+$3.50reel
of
1000
NS2ZXYTT
DS90C383MTD
BBBBB
3-9 weeks7500

Obsolete Parts

Obsolete PartAlternate Part or SupplierSourceLast Time Buy Date
DS90C383SLC

NONE
03/03/2004
DS90C383SLCX

NONE
03/03/2004

General Description

The DS90C383 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF384 receiver converts the LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec. The transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge transmitter will inter-operate with a Falling edge receiver (DS90CF384) without any translation logic. Both devices are also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint compared to the TSSOP package.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

Features

  • 20 to 65 MHz shift clock support
  • Programmable transmitter (DS90C383) strobe select (Rising or Falling edge strobe)
  • Single 3.3V supply
  • Chipset (Tx + Rx) power consumption < 250 mW (typ)
  • Power-down mode (< 0.5 mW total)
  • Single pixel per clock XGA (1024×768) ready
  • Supports VGA, SVGA, XGA and higher addressability.
  • Up to 227 Megabytes/sec bandwidth
  • Up to 1.8 Gbps throughput
  • Narrow bus reduces cable size and cost
  • 290 mV swing LVDS devices for low EMI
  • PLL requires no external components
  • Low profile 56-lead TSSOP package.
  • Also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package
  • Falling edge data strobe Receiver
  • Compatible with TIA/EIA-644 LVDS standard
  • ESD rating >7 kV
  • Operating Temperature: -40°C to +85°C

Reliability Metrics

Part Number Process Early Failure Rate - Rejects Sample Size (EFR) PPM * Rel. Rejects Device Hours Long Term Failure Rates (FITS) MTTF
DS90C383MTDCS3509200003000001284821603
DS90C383MTDXCS3509200003000001284821603

For more information on Reliablitity Metrics, please click here.


Application Notes

TitleSize in KbytesDate
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AN-1085: Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines 304 Kbytes 24-Jun-99 View Online Download Receive via Email
Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines (JAPANESE)
192 Kbytes   View Online Download Receive via Email

If you have trouble printing or viewing PDF file(s), see Printing Problems.

[Information as of 15-Jan-2004]