DS90CF388A Product Folder |
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| General Description |
Features | Datasheet | Package & Models |
Samples & Pricing |
Reliability Metrics |
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| Title | Size in Kbytes | Date | View Online |
Download |
Receive via Email |
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| DS90C387A DS90CF388A Dual Pixel LVDS Display Interface FPD-Link | 416 Kbytes | 7-Oct-02 | View Online | Download | Receive via Email |
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If you have trouble printing or viewing PDF file(s), see Printing Problems. |
| Part Number | Package | Status | Models | Samples & Electronic Orders | Budgetary Pricing | Std Pack Size | Package Marking | |||||
| Type | Pins | MSL/Lead-Free Availability | Lead Time | Qty | SPICE | IBIS | Qty | $US each | ||||
| DS90CF388AVJD | TQFP | 100 | Status | Full production | N/A | N/A | 1K+ | $5.50 | tray of 90 | NS2ZXYYTT DS90CF388AVJD BBBBB | ||
| 3-10 weeks | 2000 | |||||||||||
| DS90CF388AVJDX | TQFP | 100 | Status | Full production | N/A | N/A | 1K+ | $5.50 | reel of 1000 | NS2ZXYYTT DS90CF388AVJD BBBBB | ||
| 3-10 weeks | 2000 | |||||||||||
The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage Differential Signalling) data streams. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 784Mbps, providing a total throughput of 5.7Gbps (714 Megabytes per second). The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive. To increase bandwidth, the maximum pixel clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. The DS90C387A transmitter provides a second LVDS output clock. Both LVDS clocks are identical. This feature supports backward compatibility with the previous generation of FPD-Link Receivers - the second clock allows the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit FPD-Link receivers. This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the "Applications Information" section of this datasheet. |
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| Part Number | Process | Early Failure Rate - Rejects | Sample Size (EFR) | PPM * | Rel. Rejects | Device Hours | Long Term Failure Rates (FITS) | MTTF |
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| DS90CF388AVJD | CS35 | 0 | 9200 | 0 | 0 | 300000 | 12 | 84821603 |
| DS90CF388AVJDX | CS35 | 0 | 9200 | 0 | 0 | 300000 | 12 | 84821603 |
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