DS90CF384 Product Folder |
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| General Description |
Features | Datasheet | Package & Models |
Samples & Pricing |
Reliability Metrics |
Application Notes |
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| Title | Size in Kbytes | Date | View Online |
Download |
Receive via Email |
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| DS90C383 DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz | 365 Kbytes | 14-Nov-00 | View Online | Download | Receive via Email |
| DS90C383 DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz (JAPANESE) |
220 Kbytes |
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| Part Number | Package | Status | Models | Samples & Electronic Orders | Budgetary Pricing | Std Pack Size | Package Marking | |||||
| Type | Pins | MSL/Lead-Free Availability | Lead Time | Qty | SPICE | IBIS | Qty | $US each | ||||
| DS90CF384MTD | TSSOP | 56 | Status | Full production | N/A | 90cf384.ibs | 1K+ | $3.50 | rail of 34 | NS2ZXYTT DS90CF384MTD BBBBB | ||
| 3-8 weeks | 7000 | |||||||||||
| DS90CF384MTDX | TSSOP | 56 | Status | Full production | N/A | N/A | | 1K+ | $3.50 | reel of 1000 | NS2ZXYTT DS90CF384MTD BBBBB | |
| 4-8 weeks | 5000 | |||||||||||
| DS90CF384SLC | FBGA | 64 | Status | Lifetime buy | N/A | N/A | | 1K+ | $4.00 | tray of 360 | NS2ZXYTT DS90CF384 SLC BBBBB | |
| 3-6 weeks | 300 | |||||||||||
| DS90CF384SLCX | FBGA | 64 | Status | Lifetime buy | N/A | N/A | 1K+ | $4.00 | reel of 2000 | NS2ZXYTT DS90CF384 SLC BBBBB | ||
| 3-10 weeks | 500 | |||||||||||
| Obsolete Part | Alternate Part or Supplier | Source | Last Time Buy Date |
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| DS90CF384ASLC | | NONE | 03/03/2004 |
| DS90CF384ASLCX | | NONE | 03/03/2004 |
| DS90CF384SLC | 65101 RECEIVER | CHIPS & TECHNOLOGIES | 03/03/2004 |
| DS90CF384SLC | SN75LVDS82 | TEXAS INSTRUMENTS | 03/03/2004 |
| DS90CF384SLC | THC63LVDF84 | THINE | 03/03/2004 |
| DS90CF384SLCX | 65101 RECEIVER | CHIPS & TECHNOLOGIES | 03/03/2004 |
| DS90CF384SLCX | SN75LVDS82 | TEXAS INSTRUMENTS | 03/03/2004 |
| DS90CF384SLCX | THC63LVDF84 | THINE | 03/03/2004 |
The DS90C383 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF384 receiver converts the LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec. The transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge transmitter will inter-operate with a Falling edge receiver (DS90CF384) without any translation logic. Both devices are also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint compared to the TSSOP package. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. |
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| Part Number | Process | Early Failure Rate - Rejects | Sample Size (EFR) | PPM * | Rel. Rejects | Device Hours | Long Term Failure Rates (FITS) | MTTF |
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| DS90CF384MTD | CS35 | 0 | 9200 | 0 | 0 | 300000 | 12 | 84821603 |
| DS90CF384MTDX | CS35 | 0 | 9200 | 0 | 0 | 300000 | 12 | 84821603 |
| DS90CF384SLC | CS35 | 0 | 9200 | 0 | 0 | 300000 | 12 | 84821603 |
| DS90CF384SLCX | CS35 | 0 | 9200 | 0 | 0 | 300000 | 12 | 84821603 |
| Title | Size in Kbytes | Date | View Online |
Download |
Receive via Email |
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| AN-1085: Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines | 304 Kbytes | 24-Jun-99 | View Online | Download | Receive via Email |
| Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines (JAPANESE) |
192 Kbytes |
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If you have trouble printing or viewing PDF file(s), see Printing Problems. |
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