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 Products > Analog - Interface > LVDS Circuits > Line Drivers, Receivers and Transceivers > DS90LV049

DS90LV049  Product Folder

3V LVDS Dual Line Driver with Dual Line Receiver
Generic P/N 90LV049
General
Description
Features Datasheet Package
& Models
Samples
& Pricing
Reliability
Metrics

Parametric Table Parametric Table
Temperature Min (deg C) -40 
Temperature Max (deg C) 85 
Supply Voltage (Volt) 3.30 
OtherSupply Voltage
Drivers ()
Receivers ()
Data Rate (Mbps) 400 
Skew (ns) .05 

Datasheet

TitleSize in KbytesDate
View Online

Download

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DS90LV049 3V LVDS Dual Line Driver with Dual Line Receiver 230 Kbytes 20-Mar-03 View Online Download Receive via Email
DS90LV049 3V LVDS Dual Line Driver with Dual Line Receiver (JAPANESE)
432 Kbytes   View Online Download Receive via Email

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Package Availability, Models, Samples & Pricing

Part NumberPackageStatusModelsSamples &
Electronic
Orders
Budgetary PricingStd
Pack
Size
Package
Marking
TypePinsMSL/Lead-Free AvailabilityLead
Time
QtySPICEIBISQty$US each
DS90LV049TMTTSSOP16StatusFull productionN/Ads90lv049tmtc.ibsSamples
Buy Now
1K+$1.29rail
of
92
NSZXYTT
90LV049
TMT
2-3 weeks1000
DS90LV049TMTXTSSOP16StatusFull productionN/AN/A 
Buy Now
1K+$1.29reel
of
2500
NSZXYTT
90LV049
TMT
5-7 weeks250000

General Description

The DS90LV049 is a dual CMOS flow-through differential line driver-receiver pair designed for applications requiring ultra low power dissipation, exceptional noise immunity, and high data throughput. The device is designed to support data rates in excess of 400 Mbps utilizing Low Voltage Differential Signaling (LVDS) technology.

The DS90LV049 drivers accept LVTTL/LVCMOS signals and translate them to LVDS signals. On the other hand, the receivers accept LVDS signals and translate them to 3 V CMOS signals. The LVDS input buffers have internal failsafe biasing that places the outputs to a known H (high) state for floating receiver inputs. In addition, the DS90LV049 supports a TRI-STATE function for a low idle power state when the device is not in use.

The EN and EN# inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four gates.

Features

  • Up to 400 Mbps switching rates
  • Flow-through pinout simplifies PCB layout
  • 50 ps typical driver channel-to-channel skew
  • 50 ps typical receiver channel-to-channel skew
  • 3.3 V single power supply design
  • TRI-STATE output control
  • Internal fail-safe biasing of receiver inputs
  • Low power dissipation (70 mW at 3.3 V static)
  • High impedance on LVDS outputs on power down
  • Conforms to TIA/EIA-644-A LVDS Standard
  • Industrial operating temperature range (-40°C to +85°C)
  • Available in low profile 16 pin TSSOP package

Reliability Metrics

Part Number Process Early Failure Rate - Rejects Sample Size (EFR) PPM * Rel. Rejects Device Hours Long Term Failure Rates (FITS) MTTF
DS90LV049TMTCMOS721420014108000005226190940
DS90LV049TMTXCMOS721420014108000005226190940

For more information on Reliablitity Metrics, please click here.


[Information as of 15-Jan-2004]